Telegraphy – Systems – Line-clearing and circuit maintenance
Patent
1975-04-24
1976-11-16
Griffin, Robert L.
Telegraphy
Systems
Line-clearing and circuit maintenance
325 58, 179 15BS, H04L 700
Patent
active
039925803
ABSTRACT:
In a digital communications system having widely dispersed nodes transmitg between each other, a method and apparatus for synchronizing the processing of data at a node. Data transmitted between nodes is stored in speed buffers. The output of each buffer at a node is connected to the nodal processor and is controlled by the nodal clock. Synchronization is accomplished by performing a periodic adjustment of the frequency of the nodal clock. This adjustment is arrived at by sampling the buffer content of each node and extracting an error signal which represents the buffer position relative to the half full buffer position. The error signal is suitably weighted by a control and summed with all other weighted buffer error signals to produce a total error signal, which is added linearly to the original initial condition of the nodal clock and converted to an equivalent frequency.
REFERENCES:
patent: 3453594 (1969-07-01), Jarvas
patent: 3467779 (1969-09-01), Duerdoth
patent: 3652800 (1972-03-01), Dooley
patent: 3873773 (1975-03-01), Guy, Jr.
Bittel Raymond H.
Helm Harry A.
Raffensperger Maurice J.
Agovino Frank R.
Gapcynski William G.
Griffin Robert L.
Neureither Lawrence A.
Ng Jin F.
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