Discontinuous nitride structure for non-volatile transistors

Details Discontinuous nitride structure for non-volatile transistors Discontinuous nitride structure for non-volatile transistors

2002-12-09

2004-12-07

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

C257S239000

Reexamination Certificate

active

06828607

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to multiple independent bit Flash memory devices, and more particularly with charge sharing in multiple independent bit Flash memory devices.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates the architecture of a multiple independent bit Flash memory cell. This architecture, known as the MirrorBit™ Architecture developed by Advanced Micro Devices™, comprises a gate
102
, a source region
104
, a drain region
106
, and a body region
108
. The gate
102
comprises a first layer of oxide
116
, a layer of nitride
114
, a second layer of oxide
112
, and a layer of polysilicon
110
. This single cell
100
is capable of storing two independent bits, stored as charge at the regions
118
and
120
at either side of the interface between the first oxide layer
116
and the nitride layer
114
. It uses a symmetric transistor with similar source
104
and drain
106
.
However, to ensure reliability, the channel length, i.e., the length of the gate
102
, need to be a certain minimum length. Otherwise, charge sharing between the regions
118
and
120
may occur, and the bits stored there may become lost. This problem hinders the ability to provide greater density in Flash memories comprising MirrorBit-like Flash cells.
Accordingly, there exists a need for a method and device for reducing the potential for charge sharing in multiple independent bit Flash memory cells. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A multiple independent bit Flash memory cell has a gate that includes a first oxide layer, a discontinuous nitride layer on the first oxide layer, a second oxide layer on the discontinuous nitride layer and the first oxide layer, and a polysilicon layer on the second oxide layer. The discontinuous nitride layer has regions residing at different portions of the layer. These portions are separated by the second oxide layer. Thus, with a smaller channel length, charge that otherwise would migrate from one region to the other and/or strongly influence its neighboring bit is blocked/impeded by the second oxide layer. In this manner, the potential for charge sharing between the regions is reduced, and a higher density chip multiple independent bit Flash memory cells may be provided.


REFERENCES:
patent: 5923978 (1999-07-01), Hisamune

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