Discharge control circuit of batteries

Details Discharge control circuit of batteries Discharge control circuit of batteries

2001-01-26

2002-02-12

Toatley, Gregory (Department: 2838)

Electricity: battery or capacitor charging or discharging

Battery or cell discharging

Regulated discharging

Reexamination Certificate

active

06346795

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a discharge control circuit for a battery, and more particularly, to a discharge control circuit that prevents an over-discharge of a battery incorporated in a portable electric device.
In recent years, many portable electronic devices have employed lithium ion batteries, and extending the life of such battery will require securely preventing an over-discharge of the battery.
FIG. 1
is a schematic diagram of a conventional discharge control circuit
100
. A battery
1
that provides a power supply for a portable electric device includes a lithium ion battery in which three cells
2
a
,
2
b
,
2
c
are connected in series.
The discharge control circuit
100
controls a discharge current flowing in a portable electric device from the battery
1
. The control circuit
100
includes a control circuit
3
, a discharge control switch
4
connected to the control circuit
3
, and a capacitor
5
connected to the control circuit
3
. The switch
4
and the capacitor
5
are externally mounted.
The discharge control switch
4
is a P-channel MOS transistor. The positive terminal of the battery
1
is connected to an output terminal t
1
via the discharge control switch
4
, and the negative terminal thereof is connected to the GND terminal and an output terminal t
2
.
When the discharge control switch
4
is turned on, a power supply voltage and a discharge current are supplied to the portable electric device from the output terminals t
1
, t
2
. When the portable electric device is started to operate, a supply voltage Vcc, which depends on a power supply circuit of the portable electric device, is supplied between the output terminals t
1
, t
2
.
The discharge control switch
4
is controlled by a control signal Dout from the control circuit
3
. The negative terminals of comparators
6
a
,
6
b
,
6
c
of the control circuit
3
are connected to the positive terminals of the cells
2
a
,
2
b
,
2
c
. The positive terminals of the comparators
6
a
,
6
b
,
6
c
are supplied with a reference voltage Vth that is higher by a specific amount than the voltages at the negative terminals of the cells
2
a
,
2
b
,
2
c.
The reference voltage Vth is set at, for example, 2.8 V in relation to the cell voltage Vce of 4.2 V when the cells
2
a
,
2
b
,
2
c
are fully charged.
When the cell voltages Vce of the cells
2
a
-
2
c
exceed 2.8 V, the comparators
6
a
-
6
c
generate L-level comparator output signals. When the cell voltages Vce of the cells
2
a
-
2
c
are equal to or lower than 2.8 V, the comparators
6
a
-
6
c
generate H-level comparator output signals.
The comparator output signals are supplied to a NOR gate
7
a
, and the output signal of the NOR gate
7
a
is supplied to the first input terminal of an OR gate
8
a
and to the first input terminal of an AND gate
9
a
. When all of the comparator output signals are at L-level, the output signal of the NOR gate
7
a
goes high. The comparators
6
a
-
6
c
and the NOR gate
7
a
form a cell voltage detector
15
.
The output signal of the OR gate
8
a
is supplied to the gate of an N-channel MOS transistor Tr
1
. The drain (node N
1
) of the NMOS transistor Tr
1
is connected to the first terminal of the capacitor
5
and to a current source
10
that supplies a current I
1
. The second terminal of the capacitor
5
is connected to the GND.
When the transistor Tr
1
is turned on by the OR gate
8
a
with H-level output signal, the current I
1
supplied by the current source
10
flows through the transistor Tr
1
as a drain current. When the transistor Tr
1
is turned off, the current I
1
charges the capacitor
5
, and the voltage of the node N
1
increases accordingly.
The node N
1
is connected to the set terminal S of a latch circuit
11
. When the voltage of the node N
1
is at the H-level, the output terminal Q of the latch circuit
11
delivers the latch output signal Dout at the H-level.
The reset terminal R of the latch circuit
11
is supplied with the output signal from the AND gate
9
a
. When output signal of the AND gate
9
a
is at the H-level, the latch output signal Dout goes low. When an H-level signal is supplied to the set terminal S and to the reset terminal R, the latch circuit
11
outputs the L-level latch output signal Dout.
The latch output signal Dout is supplied to the second input terminal of the OR gate
8
a
, an inverter circuit
12
a
, and the gate of the discharge control switch
4
. When the latch output signal Dout is at the L-level, the discharge control switch
4
is turned on, and an output voltage Voc, which is substantially equal to the battery supply voltage Vcc, and a discharge current are supplied to the load circuit from the output terminal t
1
.
The output signal of the inverter circuit
12
a
is supplied to the first input terminal of a NOR gate
7
b
, and the output voltage Voc of the output terminal t
1
is supplied to the second input terminal of the NOR gate
7
b
. The output signal of the NOR gate
7
b
is supplied to the gate of a P-channel MOS transistor Tr
2
. The source of the transistor Tr
2
is supplied with the supply voltage Vcc from the battery
1
, and the drain of the transistor Tr
2
is connected to a bias generating circuit
13
.
When the voltage Voc at the output terminal t
1
becomes higher than the threshold Nth of the NOR gate
7
b
, or when the latch output signal Dout and output signal of the NOR gate
7
b
are at the L-level, the transistor Tr
2
is turned on to supply the bias generating circuit
13
with the supply voltage Vcc.
When supplied with the supply voltage Vcc, the bias generating circuit
13
supplies bias voltages to the current source
10
and the comparators
6
a
-
6
c.
The second input terminal of the AND gate
9
a
is supplied with the output voltage Voc. The AND gate
9
a
has the same threshold as the NOR gate
7
b
. The OR gate
8
a
, the transistor Tr
1
, the current source
10
, the capacitor
5
, and the AND gate
9
a
form a delay time setting circuit
14
.
In the discharge control circuit
100
, when each of the cell voltages Vce of the cells
2
a
-
2
c
of the battery
1
is higher than the reference voltage Vth, all of output signals of the comparator are at the L-level, and output signal of the NOR gate
7
a
is at the H-level. Accordingly, the output signal of the OR gate
8
a
is at the H-level, the transistor Tr
1
is turned on, and the current I
1
supplied from the current source
10
flows through the transistor Tr
1
as a drain current. As the result, the voltage of the node N
1
and the latch output signal Dout are at the L-level. The latch output signal Dout at the L-level turns the discharge control switch
4
on, which supplies the load circuit with the power supply voltage Vcc from the battery
1
via the output terminal t
1
. At this time, since the voltage Voc at the output terminal t
1
is at the H-level, both the input terminals of the AND gate
9
a
are supplied with the H-level signals, and the H-level AND gate
9
a
output signal is supplied to the reset terminal R of the latch circuit
11
, which holds the latch output signal Dout at the L-level.
Since the NOR gate
7
b
is supplied with the H-level voltage Voc and the H-level inverter circuit
12
a
output signal, the output signal of the NOR gate
7
b
is at the L-level, the transistor Tr
2
is turned on, and the bias generating circuit
13
is supplied with the supply voltage Vcc.
As shown in
FIG. 2
, when at least one of the cell voltages Vce of the cells
2
a
-
2
c
becomes lower than the reference voltage Vth, at least one of the comparator output signals is at the H-level. Since the output signal of the NOR gate
7
a
is at the L-level accordingly, the input terminals of the OR gate
8
a
are supplied with the L-level signals, and the transistor Tr
1
is turned off. Thus, the current source
10
supplies the current I
1
to charge the capacitor
5
, therefore increasing the voltage of the node N
1
gradually.
When the voltage of the node N
1
reaches the threshold Lth of the set terminal S of

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