Patent
1994-09-09
1997-12-09
Chan, Eddie P.
395464, G06F 1208
Patent
active
056969317
ABSTRACT:
A disc controller services a host "read" command, without intervention by the disc controller's microcontroller, if the requested data is found in the disc controller's cache. The disc controller stores at least one cache entry. Each cache entry includes an address, a logical Bit, a valid Bit and a set of four buffer parameters: upper limit address, base address, pointer to the sector count and sector count. Each host command is decoded by the disc controller, and if the command is a "read" command the address in the cache entry is compared against the address in the host command. If the addresses match and the cache entry address is marked as being valid by its Valid bit, a "cache hit" signal is generated and the disc controller starts transferring the data requested by the host without waiting for the disc controller's microprocessor to process the host command. In particular, a sequencer and data transfer circuitry automatically generate a host interrupt request signal and transfer to the host at least a subset of the requested set of data blocks specified by each read command when a cache hit signal is generated. The disc controller includes circuitry for updating the information stored in the cache entry so that said updated information stored in the cache entry identifies data blocks in the cache sequentially subsequent to those data blocks transferred to the host.
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Duncan Kathleen Anne
Lum Marvin Mang-Yin
Reddy Prafulla Bollampali
Robinson Don Michael
Chan Eddie P.
Ellis Kevin L.
Seagate Technology Inc.
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