Disabled memory sections for degraded operation of a vector supe

Details Disabled memory sections for degraded operation of a vector supe Disabled memory sections for degraded operation of a vector supe

1990-11-27

1994-07-05

Beausoliel, Jr., Robert W.

Excavating

371 111, 371 102, G06F 1318

Patent

active

053275500

ABSTRACT:
Maintenance modes of operation of a multiprocessing vector supercomputer system are disclosed. The modes allow diagnostics to run on a failed portion of the system while simultaneously allowing user tasks to run in a degraded performance mode. This is accomplished by assigning a processor or a group of processors to run diagnostics on an assigned portion of memory, while the operating system and user tasks are run in the remaining processors in the remaining portion of memory. In this manner, the diagnostics can isolate the problem without requiring complete shut down of the user task, while at the same time protecting the integrity of the operating system. The result is significantly reduced preventive maintenance down time, more efficient diagnosis of hardware failures, and a corresponding increase in user task run time.

REFERENCES:
patent: 4128880 (1978-12-01), Cray, Jr.
patent: 4503535 (1985-03-01), Budde et al.
patent: 4636942 (1987-01-01), Chen et al.
patent: 4661900 (1987-04-01), Chen et al.
patent: 4745545 (1988-05-01), Schiffleger
patent: 4754398 (1988-06-01), Pribnow
patent: 4757474 (1988-07-01), Fukushi et al.
patent: 4884194 (1989-11-01), Krol et al.
patent: 5142638 (1992-08-01), Schiffleger
patent: 5148540 (1992-09-01), Beardsley et al.
patent: 5201053 (1993-04-01), Benhase et al.
Patent Abstracts of Japan, vol. 13, No. 200 (P-869) May 12, 1989 & JP,A,1 021 564 (Fujitsu Ltd.) Jan. 24, 1989.
Proceedings of the 1986 IBM Europe Institute Seminar on Parallel Computing, Aug. 11-15, 1988 pp. 149-163, North-Holland, Amsterdam, NL; E. Maehle: "Multiprocessor Testbed Dirmu 25: Efficiency and Fault Tolerance" see p. 158, line 10 p. 161, line 22; FIGS. 2, 9, 10.
Proceedings of the International Conference on Parallel Processing, Aug. 17-21, 1987, pp. 885-888, Pennsylvania State Univ. Press, London, GB; V. Cherkassky et al.: "Graceful Degradation of Multiprocessor Systems" see p. 885, left column, line 49-p. 886, right column, line 42; FIGS. 1,2.

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