Directory test error mode control apparatus

Details Directory test error mode control apparatus Directory test error mode control apparatus

1983-06-30

1985-12-31

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

045625360

ABSTRACT:
A multilevel set associative cache system whose directory and cache store organized into levels of memory locations. Round robin replacement apparatus is used to identify in which level information is to be replaced. The directory includes error checking apparatus for generating address check bits which are written into directory locations together with addresses. Control apparatus in response to error signals from the error checking apparatus degrades cache operation to those levels detected to be free from errors. Test error mode control apparatus which couples to the replacement and check bit apparatuses causes the address check bits to be selectively forced to incorrect values in response to commands received from a central processing unit enabling the verification of both the checking and control apparatus without interference from other operations initiated by the central processing unit.

REFERENCES:
patent: 4392201 (1983-07-01), Brown et al.

Affiliated with

Also associated with

Rating

Directory test error mode control apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Directory test error mode control apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Directory test error mode control apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1027923