Patent
1997-06-23
1999-11-30
Teska, Kevin J.
39550007, G06F 1750
Patent
active
059957352
ABSTRACT:
An improved method for routing interconnect lines in a VLSI chip using repeaters. First, an optimal virtual assignment of the repeater locations is determined according to a suitable method. The "virtual" assignment is the ideal location irrespective of where logic blocks which could form a repeater cell might located. Next, repeaters are assigned to physical locations close to the optimal virtual locations. Finally, an optimal global routing is done using the physical locations of the repeaters. The optimal global routing revises the original global routing upon which the original optimal virtual assignment of repeaters was done. Preferably, blocks of circuitry and routing channels are identified first. Instead of simply routing the interconnect lines through the channels, a portion of the interconnect lines are routed through available spaces in the blocks themselves. This will reduce the number of turns required both through the channels and to reach a repeater. By routing through the blocks, repeaters can be placed at the entry or exit point on the block, eliminating the need for providing L or U-turns to a repeater from a channel.
REFERENCES:
patent: 5410491 (1995-04-01), Minami
patent: 5557779 (1996-09-01), Minami
patent: 5838580 (1998-11-01), Srivatsa
patent: 5838581 (1998-11-01), Kuroda
Garbowski Leigh Marie
Sun Microsystems Inc.
Teska Kevin J.
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