Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
2003-02-21
2004-12-28
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
C327S012000
Reexamination Certificate
active
06836154
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to phase detectors, and more specifically to direction sensitive phase detectors.
BACKGROUND OF THE INVENTION
Phase detectors are found in numerous applications of all modern technologies. They are widely used in areas of electronics and in different fields of communication, in particular the field of telecommunication.
Basically, a phase detector is an arrangement for measuring a phase difference between two input signals. In a typical application, the phase detector is used in a phase-locked loop (PLL). A phase-locked loop is generally a circuit for synchronizing an output signal of the loop with an input reference signal in frequency as well as in phase, and it is often used in retiming and frequency synthesization applications. In order to accomplish the synchronization of the reference signal and the loop output signal, a phase detector is required for continuously measuring the phase difference between the two signals, and the measured phase difference is utilized for controlling the frequency of the loop output signal.
FIG. 1
is a schematic block diagram of a conventional phase-locked loop. The PLL
10
basically includes a phase detector (PD)
13
, a loop filter (LF)
14
and an output clock signal source such as a voltage-controlled oscillator (VCO)
15
. The phase detector
13
is generally responsive to the output signal (V) of the VCO
15
and an incoming reference clock signal (R) provided by a reference clock signal source
11
for generating a phase difference representing signal. The loop filter
14
averages or integrates the phase difference representing signal to produce a control voltage (V
C
) for the VCO
15
. For generality, it should be understood that the PLL may very well be associated with frequency dividers, for example a first divider
12
for the reference clock signal from the reference clock source
11
and a second divider
16
for the output clock signal of the VCO
15
in the feedback loop.
The synchronization is achieved by frequency correction of the loop output signal in response to the phase difference measured by the phase detector. In the synchronized state, also referred to as the locked state or steady state, there is a predefined mandatory phase relation between the VCO output clock signal and the input reference clock signal, and there is generally no average frequency offset between the signals. However, if there is an instantaneous phase jump, or if a phase difference starts to build up, e.g. due to a frequency offset between the loop output signal and the reference signal, the phase-locked state is lost and the inherent control mechanism of the PLL strives to eliminate the frequency offset and find the phase-locked state again.
Of special interest is the impact of different phase detector (PD) choices on the overall PLL performance such as lock-in procedure and range, static phase error at lock and sensitivity to input clock anomalies. Two phase detectors are commonly used, the simple XOR gate (digital multiplier) and the direction sensitive phase-frequency detector (PFD).
Digital Multiplier
For the XOR gate based PLL, lock acquisition is totally unaided. Lock acquisition starts in a random direction until the proper direction is stumbled onto and ends when the loop filter has been charged to proper voltage for nominal output frequency and zero phase error at the phase detector input. If the reference clock behaves abnormal with a large content of harmonics to the fundamental reference clock frequency, a PLL utilizing an XOR gate PD may falsely lock to a harmonic since it has no frequency selection capability. On the other hand the averaging nature of the XOR gate PD reduces the PLL sensitivity to noise and other disturbances.
Phase Frequency Detector
However, to obtain a more structured lock acquisition procedure rather than pure random operation, it is advisable to use a phase frequency detector (PFD), which differentiates between frequency and pure phase mismatches and introduces so-called direction sensitivity. The phase frequency detector is a multi-state detector, which is capable not only of measuring the magnitude of the phase difference, but also of indicating the lead/lag relation between the clock signals. In this way, the frequency of the loop output signal can generally be altered directly in the right direction without losing valuable time.
FIG. 2
is a schematic state diagram representation of state machine for a conventional phase frequency detector. The PFD state machine has four different states denoted 00/LL, 01/LH, 10/HL and 11/HH, and alternates between two distinct control loops depending on the lead/lag relation between the clock signals. The transition conditions are associated with the signal states of the input clock signals to the PFD state machine, and indicated along the transition lines in the state diagram.
FIG. 3
is a circuit diagram of a typical implementation of the PFD state machine of FIG.
2
. The PFD implementation
20
is based on D flip-flops (DFFs)
21
,
22
and a NAND gate
23
. The phase detector is triggered by positive edge transitions, and fed by a supply voltage (V
CC
). The phase detector has a step-up frequency output terminal (retard phase terminal) u
R
and a step-down frequency output terminal (advance phase terminal) u
V
. As indicated in
FIG. 2
, the physical phase detector output voltages u
V
and u
R
, coded as L (Low) or H (High), are associated with the state variables Q
V
and Q
R
, respectively.
In the PLL, the frequency of the loop output signal is adjusted when the loop filter integrator is charged or discharged by the phase frequency detector output. Irrespective of the initial state of the PFD, only the DFF that receives a positive edge transition on the associated PFD input will be active with a high Q output. Whenever one of the input clocks lag in frequency, only one PFD output terminal is active to signal the direction of the regulation to speed up the clock with lower frequency. For example, if the reference clock is ahead of the VCO clock, then u
R
is high (H) with U
V
constantly low (L) corresponding to the state 01/LH in the state diagram of
FIG. 2
, and the loop filter integrator is charged, thus increasing the VCO control voltage and the VCO output frequency. For a lagging reference clock the situation is reversed and u
R
is low (L) with u
V
high (H) corresponding to the state 10/HL so that the loop filter integrator is drained of charge and the VCO output frequency is lowered. Due to the asynchronous implementation there is an intermediate state 11/HH that is implicitly formed from the finite reset time of the state variables (DFFs) in the transitions to the ground state 00/LL. Missing clock pulses in the reference clock will be interpreted by the PFD as a frequency mismatch, and to prevent the PLL from reacting with abrupt output frequency changes a resonant circuit, a so-called Q-tank, is normally arranged prior to the reference clock input of the PFD.
Compared to a PLL based on a multiplier phase detector that averages the phase difference with no built in directivity, a more well defined lock acquisition procedure is obtained with a direction sensitive PFD type detector. However, conventional PFD type detectors suffer from problems with so-called phase inversion.
Phase Inversion
For a PLL based on a direction sensitive PFD detector there are always at least two different trajectories or paths that lead to phase lock from a given initial phase relation between the reference clock and the loop output clock. Since the loop output clock may be advanced or retarded the phase difference (&thgr;
e
) is reduced to zero either the shortest distance (&thgr;
e
) or the longer distance (360°−&thgr;
e
) from the complementary direction. For the common phase frequency detector that has a linear range including both possibilities, a disturbance may shift the phase detector state such that the control system is forced to minimize the very large complementary phase error producing
Callahan Timothy P.
Cox Cassandra
Nixon & Vanderhye P.C.
Telefonaktiebolaget LM Ericsson (publ)
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