Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2005-10-17
2008-10-07
Hur, J. H. (Department: 2824)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S222000, C365S230030, C365S189040, C365S233100
Reexamination Certificate
active
07433261
ABSTRACT:
A memory includes a row address latch. The row address latch includes a first stage configured to latch a row address for a memory read or write operation, and a second stage configured to latch a row address for a memory bank auto-refresh. The row address latch provides the row address from the first stage in response to an activate command and provides the row address from the second stage in response to a directed auto-refresh command.
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“Corresponding Korean patent application Notice of Allowance issued on Apr. 15, 2008.”.
Freebern Margaret Clark
Szczypinski Kazimierz
Dicke Billig & Czaja, PLLC
Hur J. H.
Infineon - Technologies AG
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