Direct moat self-aligned field oxide technique

Details Direct moat self-aligned field oxide technique Direct moat self-aligned field oxide technique

1985-10-21

1987-08-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 61, H01L 21465

Patent

active

046851941

ABSTRACT:
The process of the present invention produces CMOS bulk circuits allowing any treatment of the field oxide up to and including the channel edge; allows p-field boron implant to increase parasitic threshold eliminates the bird's beak oxide encroachment which reduces channel width and recessed oxide along the channel edge; provides for a self-aligned p-field implant; and provides for a spacer use on a self-aligned p-field implant to offset effects of side diffusion and oxide undercut. (1) Growing a field oxide layer including any specialized hardening techniques thereto on a silicon wafer; (2) Depositing a material which will serve as an implant mask such as aluminum; (3) Etching this layer to leave shapes where the thin oxide gate regions are to be; (4) Depositing a spacer material such as sputtered nitride onto the shapes; (5) Etching the spacer material; (6) Depositing a field implant mask; (7) Etching the implant mask; (8) Implanting the field regions; (9) Stripping the implant mask; (10) Stripping the spacer material if used; (11) Depositing a secondary masking layer such as Ti-W or W; (12) Bias sputtering away secondary masking material at edges of aluminum shapes; (13) Removing aluminum shapes using secondary material as a mask; (14) Etching oxide under aluminum shapes to reach the silicon wafer; (15) Stripping secondary masking layer; (16) Growing gate oxide; (17) Removing field oxide layer to expose source and drain regions in the wafer; and (18) Placing electrodes onto the drain, source, and gate regions.

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