Multiplex communications – Communication techniques for information carried in plural... – Adaptive
Reexamination Certificate
1998-08-24
2001-08-14
Cangialosi, Salvatore (Department: 2732)
Multiplex communications
Communication techniques for information carried in plural...
Adaptive
C370S474000
Reexamination Certificate
active
06275504
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a direct memory read and cell transmission apparatus for an ATM (Asynchronous Transfer Mode) cell segmentation system, and in particular, to an improved direct memory read and cell transmission apparatus for an ATM cell segmentation system which is capable of directly reading and transmitting data from a PCI (Peripheral Component Interface) BUS of the system to which an ATM cell segmentation system is attached, whereby it is possible to receive word data stream with start address and size information given in byte unit by receiving bytes from the data formed in another word unit and forming an ATM cell using other information and further implementing automatic padding and stop request handling.
2. Description of the Conventional Art
In the conventional art, the data to be transmitted are transferred to an external local memory, and an ATM processing circuit processes the data of the local memory based on a segmentation method. In this method, since a host CPU (Central Processing Unit) moves the data of a host memory to the local memory, it takes much time from the CPU for data movement.
Another method is recently disclosed, in which the ATM processing circuit actively reads data from the host memory, forms ATM cell, and then sends it to network. In this case, the host CPU transfers a control information, which corresponds to the position of the data to be transmitted, to the ATM processing circuit based on a queue, etc. In this method, in the case that the host data bus is 32 bits or 64 bits wide, since the transmit data of the host memory is not word aligned, the data can not be processed. In this case, the host CPU disadvantageously moves the data to a temporary position for aligning the data in 32 bit form. In addition, if the data to be carried by a cell is not located in a contiguous location in memory, the CPU should gather and aligne such data in the contiguous location to make the DMA information is divided between cell boundaries. In addition, the size of bytes to be padded should be computed and transferred as a control information. In this schem, the host CPU is involved in moving all, the data for word alignment and data gathering and computes the size of padding bytes, whereby the processing time of the CPU is extended.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a direct memory read and cell transmission apparatus for an ATM cell segmentation system which overcomes the aforementioned problems encountered in the conventional art.
It is another object of the present invention to provide a direct memory read and cell transmission apparatus for an ATM cell segmentation with which it is possible to let the CPU handle the transferring of a minimum control information and receiving of a status information which are used for a data transmission in such a way that the data of a CPCS-PDU (Common Convergence Sublayer-Protocol Data Unit) which is segmented into ATM cells remains as is in a host memory, so that major data transfer operation is implemented by a function unit having a direct memory access (DMA) master function for thereby gaining high performance based on a minimum use of the CPU.
It is another object of the present invention to provide a direct memory read and cell transmission apparatus for an ATM cell segmentation system which is capable of enhancing a DMA read function so that the data to be transmitted are in the host memory.
In order to achieve the above objects, there is provided a direct memory read and cell transmission apparatus for an ATM cell segmentation system according to a first embodiment of the present invention which includes a read controller for requesting a PCI memory read using a start address and byte size of an external transmission data of a host memory and reading and transferring a data from a peripheral component internal access interface; an alignment unit for extracting a predetermined byte from a data of the word unit externally transmitted together with an output signal from the read controller and aligning the same; a cell transmission unit for transmitting a byte remaining in the alignment unit in accordance with a cell transmission request signal from the read controller; a cell FIFO unit for storing the aligned word data in accordance with a write signal from the alignment unit and outputting the internal data in accordance with a read signal outputted from the cell transmission unit; an error detecting code generator for detecting an error of the signal outputted from the cell transmission unit; and a selection unit for selectively outputting an external signal, an output signal from the FIFO unit and an output signal from the cell transmission unit in accordance with a selection signal from the cell transmission unit.
In order to achieve the above objects, there is provided a direct memory read and cell transmission apparatus for an ATM cell segmentation system according to a second embodiment of the present invention which includes a segmentation circuit for reading/writing an information written in a local memory, interpreting the information, extracting an information used for combining the information and cell which are necessary for the DMA and transferring to a DMA read and cell combining circuit; and a DMA read and cell combining circuit for receiving an information used for the DMA and an information used for a cell combining operation from the segmentation circuit, generates a cell using the data transferred from the host memory, generating a cell using a data transferred from the host memory and a data used for the cell combining operation and then transferring to the segmentation circuit.
In order to achieve the above objects, there is provided a direct memory read and cell transmission apparatus for an ATM cell segmentation system according to a second embodiment of the present invention which includes a segmentation circuit for reading/writing an information from a local memory, interpreting the information, extracting an information used for combining an information and cell used for the DMA and transferring to the DMA read and cell combining circuit; and a DMA read and cell combining circuit for receiving an information used for the DMA and an information used for the cell combining operation from the segmentation circuit, performing a DMA reading operation, generating a cell using the data transmitted from the host memory and used for the cell combining operation and transferring to the segmentation circuit.
Additional advantages, objects and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
patent: 5548587 (1996-08-01), Bailey et al.
patent: 5633870 (1997-05-01), Gaytan et al.
patent: 5845153 (1998-12-01), Sun et al.
C. Brendan S. Traw, et al., “Hardware/Software Organization of a High-Performance ATM Host Interface”, IEEE Journal on Selected Areas in Communications, vol. 11, No. 2, Feb. 1993, pp. 240-253.
Gerald W. Neufeld et al., “Parallel Host Interface for an ATM Network”, IEEE Network, Jul. 1993, pp. 24-34.
Jun Jong Arm
Kim Chan
Kim Hyup Jong
Kim Jae Geun
Lee Kyou Ho
Cangialosi Salvatore
Electronics and Telecommunications Research Institute
Jacobson & Holman PLLC
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