Direct memory access revolving priority apparatus

Details Direct memory access revolving priority apparatus Direct memory access revolving priority apparatus

1983-12-01

1985-12-10

Thomas, James D.

Boots, shoes, and leggings

G06F 1300, G06F 304

Patent

active

045584125

ABSTRACT:
In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems, all connected in common to a system bus, the system bus timing is divided into a plurality of fixed times including a central processor (CPU) bus cycle and a plurality of Direct Memory Access (DMA) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles.
Particular peripheral subsystems are assigned to particular DMA channels. These DMA channels communicate with the memory subsystem on particular DMA bus cycles which are operative in a revolving priority, with the first DMA bus cycle occuring after the last DMA bus cycle of the previous sequence of DMA bus cycles.
A plurality of peripheral subsystems are wired to a particular DMA channel in a daisy chain fashion with the peripheral subsystem wired closest to the system bus having top priority. The peripheral subsystem having top priority may be wired either to relinquish the assigned DMA bus cycle after communicating with memory or "hog" the assigned DMA bus cycle.

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Gschwind, "Design of Digital Computer", Springer-Verlag, 1975, pp. 168-171.

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