Direct memory access controller with direct memory to memory tra

Details Direct memory access controller with direct memory to memory tra Direct memory access controller with direct memory to memory tra

1988-10-07

1990-05-08

Shaw, Gareth D.

Boots, shoes, and leggings

3649646, 364964, 3649483, 36494831, G06F 1202, G06F 1516, G06F 1314

Patent

active

049244272

ABSTRACT:
In a data processing system, each direct memory access controller is connected to a bus and the memory it controls, the memory being connected to a bus, bypassing the controller. The controller simultaneously generates two addresses, one for addressing the memory space it controls and another for addressing memory space controlled by another controller. Data is then passed directly from one memory space over the bus to another memory space in a single clock cycle. When a controller is acting as a bus master it causes the generation of a system, user or external signal signifying what memory space it will be permitted to access and each controller includes comparison circuits for comparing an address on the bus with one or more address space limit values, depending upon which of the three signals is received. An error signal is produced by the controller if another controller attempts to address memory space which it is not permitted to access. The controller also includes registers for storing an interrupt address, a constant value and status, and circuitry for transferring the status and constant value over the bus for storage at the interrupt address, the transfer taking place automatically upon detection of an exception.

REFERENCES:
patent: 4099231 (1978-07-01), Kotok et al.
patent: 4120043 (1978-10-01), Su
patent: 4122531 (1978-10-01), Tamaru et al.
patent: 4417318 (1983-11-01), Hirahata et al.
patent: 4466098 (1984-08-01), Southard
patent: 4495567 (1985-01-01), Treen
patent: 4545014 (1985-10-01), Oguchi
patent: 4700292 (1987-10-01), Campanini

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