Direct memory access controller handling exceptions during trans

Details Direct memory access controller handling exceptions during trans Direct memory access controller handling exceptions during trans

1992-01-30

1995-11-07

Elmore, Reba I.

395841, G06F 1326

Patent

active

054653401

ABSTRACT:
A direct memory access controller (DMAC) is provided to transfer bytes from arbitrary offset byte boundaries while performing data check operations in parallel to the movement of data in parallel through the DMA controller. The DMA controller moves data during each memory cycle and validates the moved data at the destination memory during the writing of bytes to the destination address.

REFERENCES:
patent: 4688166 (1987-08-01), Schneider
patent: 4845657 (1989-07-01), Yokota et al.
patent: 5185876 (1993-02-01), Nguyen et al.
patent: 5295250 (1994-03-01), Komoto et al.
Hardware-Assisted Byte Alignment for High-Speed Digital Communications Processors; IBM Technical Disclosure Bulletin, vol. 29, No. 2, Jul. 1986, Armonk, N.Y., US pp. 864-868.

Affiliated with

Also associated with

Rating

Direct memory access controller handling exceptions during trans does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Direct memory access controller handling exceptions during trans, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Direct memory access controller handling exceptions during trans will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-202242