Direct memory access controller

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364DIG1, 3642423, 36424231, G06F 1300, G06F 1328, G06F 1332

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active

052789659

ABSTRACT:
A direct memory access controller adaptable to control a direct memory access transfer in a data processing system which includes at least a central processing unit and a system bus, comprises a register coupled to the system bus for outputting a transfer terminate request signal which instructs a normal termination when the central processing unit is operating and a write operation is carried out with respect to the register from the central processing unit, and a transfer termination part coupled to the register for stopping to accept a new transfer request signal or stopping to generate a transfer request signal responsive to the transfer termination request signal so as to make an instructed channel inactive.

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