Boots – shoes – and leggings
Patent
1984-08-16
1989-03-07
Heckler, Thomas M.
Boots, shoes, and leggings
364900, G06F 104, G09G 100
Patent
active
048112046
ABSTRACT:
A data processing system including a central processing unit which connects to two or more buses. The buses include a memory bus connected to a main store, and to two or more I/O devices sharing common control for accesses to the main store. Priority of transfers over the memory bus is determined by priority circuit in a two-way priority between the processing unit and the common I/O devices on the memory bus. One common I/O devices is a display unit and the other common I/O device is a direct memory access disk unit. The display is periodically refreshed. Priority is always granted to the display device. Priority is granted to the disk device as a supplement to a access by the display device. The direct memory access device piggybacks on the priority of the display device.
REFERENCES:
patent: 4156904 (1979-05-01), Minowa et al.
patent: 4181933 (1980-01-01), Benysek
patent: 4257095 (1981-03-01), Nadir
patent: 4263648 (1981-04-01), Stafford et al.
patent: 4373183 (1983-02-01), Means et al.
patent: 4403303 (1983-09-01), Howes et al.
patent: 4414645 (1983-11-01), Ryan et al.
patent: 4417334 (1983-11-01), Gunderson et al.
patent: 4418343 (1983-11-01), Ryan et al.
patent: 4462028 (1984-07-01), Ryan et al.
patent: 4511965 (1985-04-01), Rajaram
patent: 4535330 (1985-08-01), Carey et al.
patent: 4556879 (1985-12-01), Tanaka
patent: 4558412 (1985-12-01), Inoshita et al.
Heckler Thomas M.
Nguyen Viet Q.
Vadem Corporation
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