Patent
1995-02-09
1997-12-02
Lane, Jack A.
395412, G06F 1200
Patent
active
056945671
ABSTRACT:
A direct mapped cache with cache locking according to one embodiment of the present invention includes a physical address latch and a multiplexing means. The multiplexing means receives the physical address from the physical address latch and exchanges a physical address tag bit with a physical address index bit to generate a cache tag address and a cache index address to divide the cache into two halves, each half servicing a contiguous address range of main memory.
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Bourekas Philip A.
Ng Andrew P.
Integrated Device Technology Inc.
Lane Jack A.
Verbrugge Kevin
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