Direct inner layer interconnect for a high speed printed...

Details Direct inner layer interconnect for a high speed printed... Direct inner layer interconnect for a high speed printed...

2001-06-26

2003-07-15

Cuneo, Kamand (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S261000, C174S255000, C174S260000, C361S792000, C361S795000, C361S760000, C439S065000

Reexamination Certificate

active

06593535

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENTS REGARDING FEDERALLY SPONSORED RESEARCH
Not applicable.
FIELD OF THE INVENTION
This invention relates generally to printed circuit boards and more particularly to multi-layer printed circuit boards which carry high speed signals.
BACKGROUND OF THE INVENTION
As is known in the art, conductive traces are formed on printed circuit boards for carrying data signals and power between components mounted on the board. Space considerations often require the use of multi-layer printed circuit boards including multiple layered dielectric substrates with conductive traces formed on each substrate. The layered substrates are held together to make a printed circuit board that has conductive traces on different levels within the board.
In order to interconnect conductive traces on different layers, conductive vias extend between layers of the multi-layer printed circuit board. For this purpose, conductive vias intersect vertically aligned pads joined to conductive traces on different layers. Conductive vias also interconnect components mounted on the board to conductive traces on inner layers of the board. More particularly, a contact of the component, such as a press-fit pin, makes contact with the conductive walls of the via and the conductive walls of the via, in turn, contact one or more pads of conductive traces on inner layers of the board. Vias which extend through all layers of a multi-layer board are sometimes referred to as through holes.
Conductive vias are formed after the layered substrates are formed into a board. The vias are typically formed by drilling holes through at least a portion of the board and plating the walls of the holes with a conductive material, such as copper. Typically, a thin layer of copper is applied by an electroless process. An electrical potential is connected to this thin layer of copper and a thicker layer of copper is deposited over the thin layer by an electrolytic deposition process. In order to ensure reliable plating of the via walls, the aspect ratio of the printed circuit board thickness to the via diameter is limited. For example, for a circuit board having a thickness on the order of 0.25 inches (6.35 mm), the diameter of a plated via must be on the order of at least 0.018 inches (0.46 mm) requiring the hole to be on the order of 0.020 inches (0.51 mm) for plating thickness on the order of 0.002 inches (0.05 mm). This minimum via diameter limits the number of vias that can be provided in a given circuit board area.
An illustrative multi-layer printed circuit board
10
having a conductive via
14
is shown in
FIG. 1
to include dielectric layers
12
a
,
12
b
, and
12
c
, with a conductive trace
16
formed on layer
12
b
. In the example, a three layer board is shown. It should be appreciated that the number of layers is selected for simplicity of illustration and the number of layers is not a limitation on the invention. However, the invention will be most useful with thicker boards. The conductive via
14
extends through a pad
17
of signal trace
16
in order to electrically interconnect to the signal trace
16
. A pin
26
of a component
28
inserted at least partially into the via
14
contacts the conductive walls of the via and thus, is electrically connected to signal trace
16
.
The high data rates of signals carried by printed circuit boards require careful attention to aspects of the circuit board structure affecting signal quality. As one example, portions of a conductive via extending beyond inner layers of the board which are interconnected to other layers and/or to a component mounted on the board, such as portion
20
of via
14
, can act as a resonant stub, causing undesirable signal reflections at certain frequencies.
One solution to this problem is to use “blind” or buried vias for interconnecting traces on inner layers of a printed circuit board. A blind via extends from the surface of a board through only a portion of the layers of a multi-layer printed circuit board. It is, however, undesirable to make blind vias of multiple depths. Buried vias are used to interconnect two interior layers of the printed circuit board. Buried vias are formed by first making a subassembly from several layers of the printed circuit board. A hole is drilled through these layers and the hole is plated. Additional substrate layers are added to the top and the bottom of the subassembly to make a complete printed circuit board. The resulting buried vias are inaccessible and increase the manufacturing complexity of the multi-layer printed circuit board.
An alternative technique for eliminating resonant stubs formed by portions of conductive vias is to remove the stub portions of the via by drilling them out of the board. For example, by drilling a hole through layers
12
b
and
12
c
concentrically around, and with a larger diameter than the via
14
, the via portion
20
extending through layers
12
b
and
12
c
is removed. However, this technique requires additional manufacturing steps.
SUMMARY OF THE INVENTION
It is an object of the invention to eliminate resonant stub portions of conductive vias in a multi-layer printed circuit board.
It is another object of the invention to provide an easily manufactured structure for making reliable electrical connection to a conductive trace on an inner layer of a multi-layer printed circuit board.
It is a further object of the invention to increase the component density achievable with a multi-layer printed circuit board.
These and other objects of the invention are achieved by providing a non-conductive via through at least a portion of a printed circuit board having a plurality of stacked dielectric layers with a conductive trace, or conductor formed on at least one inner layer. The non-conductive via intersects the conductor to expose a portion of the conductor. A conductive element extends into at least a portion of the via to contact the exposed portion of the conductor.
Because the via does not have a conductive coating, resonant stubs are not formed. A further advantage of the non-conductive via is that two conductive elements, such as contacts of two different electrical components, can be inserted into a single non-conductive via from opposite sides of the board in order to make direct electrical connection between the components and conductive traces on inner layers of the board. In this way, the circuit board density could be increased.
Generally, the conductive element is a contact of an electrical component mounted on the board. One illustrative conductive element includes an eye-of-the-needle portion configured for being press-fit into the non-conductive via. Another conductive element includes a serrated portion for contacting an inner layer trace. The conductive element may be comprised of a metal or a conductive paint or polymer.
The non-conductive via may extend through the entire board or through only a portion of the board. In one embodiment, the non-conductive via is tapered and the conductive element has a complementary taper such that the conductive element can be wedged into the non-conductive via to contact an exposed inner layer trace.
According to a further embodiment of the invention, a non-conductive via has a first, reduced diameter portion intersecting an inner layer conductor and a second, larger diameter portion located between the reduced diameter portion and a surface of the board. This “stepped” non-conductive via is adapted to receive a conductive element having a first reduced diameter portion for contacting the conductor and a second, larger diameter portion press-fit into the larger diameter portion of the via in order to mechanically attach the conductive element to the board.
With this arrangement, the portion of the conductive element in contact with the conductor can be provided with a smaller diameter than would be possible if this portion additionally provided the mechanical attachment mechanism to the board. In this way, the reduced diameter portion of the conductive element is optimiz

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