Direct-injection FIFO shift register

Details Direct-injection FIFO shift register Direct-injection FIFO shift register

1986-09-16

1987-06-09

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular input circuit

377 66, 377 80, G11C 700

Patent

active

046726462

ABSTRACT:
A FIFO shift register (100) includes a parallel data in-port (PIN) to each of its cells (101-132) and a means for managing input to determine for each cell whether it is to receive data and, if so, whether through its conventional serial in-port (SIN) or through its parallel in-port. The input manager comprises a bidirectional shift register of input manager cells arranged in one-to-one correspondence with data cells. A one-bit validity indicator stored within a given input manager cell is logically combined with asserted PUSH and PULL signals to determine the source of data for the associated data cell and its immediate successor. This arrangement not only provides greater speed by minimizing bubble-through time, but permits the FIFO shift register to be clocked. This capacity for synchronous operation permits ready VLSI implementation with concomitant advantages in economy, reliability and speed.

REFERENCES:
patent: 3212009 (1965-10-01), Parker
patent: 3838345 (1974-09-01), Schneider
patent: 3972034 (1976-07-01), Derickson et al.
patent: 4058773 (1977-11-01), Clark et al.
patent: 4156288 (1979-05-01), Spandorfer
patent: 4293919 (1981-10-01), Dasgupta et al.

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