Patent
1995-11-07
1997-12-02
Kim, Matthew M.
395842, 395494, G06F 1208, G06F 1328
Patent
active
056945752
ABSTRACT:
The computer system comprises a processor 1, a cache memory 2 of this processor, a main memory 4, an I/O device 6 directly accessible to this main memory, an I/O controller 7, and the like. It is made so that the I/O controller can execute processing to retain data consistency between the cache memory and the main memory during access to the main memory by the I/O device. The I/O controller has an address buffer 9 that retains the cache line address of the previous access by the I/O device and it is made so that the consistency maintenance operation is not executed in cases other than the first access when accesses to the main memory by the I/O device are made continuously in the same data block.
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Oba Nobuyuki
Shimizu Shigenori
International Business Machines Corp.
Kim Matthew M.
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