Direct I/O access to express bussing in a configurable logic arr

Details Direct I/O access to express bussing in a configurable logic arr Direct I/O access to express bussing in a configurable logic arr

1993-06-18

1994-06-21

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307465, 307475, H03K 19177

Patent

active

053230698

ABSTRACT:
The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a generally rectangular matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical rows of logic cells. The array further includes at least one horizontally aligned express bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned express bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array further includes a plurality of logic cell I/O pins located at the periphery of the matrix and connectable to the logic cells in the rows and columns at the periphery of the matrix. Furthermore, the array includes a plurality of express bus I/O pins directly connectable to the express busses.

REFERENCES:
patent: 4642487 (1987-02-01), Carter
patent: 5073729 (1991-12-01), Greene et al.
patent: 5079451 (1992-01-01), Gudger et al.
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5155389 (1992-10-01), Furtek

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