Boots – shoes – and leggings
Patent
1984-08-23
1988-05-24
Eng, David Y.
Boots, shoes, and leggings
G06F 1308
Patent
active
047470445
ABSTRACT:
A data processing system including an addressable main memory for storing data and directly executable microinstructions, and a central processing chip having a data interface terminal and an instruction terminal. A processor memory bus is connected between the main addressable memory and the central processing chip data interface terminal. An instruction bus is connected between the central processing chip instruction terminal and the addressable memory.
The directly executable microinstructions in the addressable main memory are fetched from the main memory by an apparatus which includes an instruction address circuit connected to the processor memory bus and the instruction bus. The instruction address circuit includes a virtual address register circuit for receiving a portion of a virtual address from the instruction bus, and a portion of the mentioned virtual address from the processor memory bus. A virtual-to-real translation circuit in the instruction address circuit translates the virtual address in the virtual address register to a real address in the addressable memory from which an executable microinstruction may be fetched.
REFERENCES:
patent: 4085448 (1978-04-01), Kogge
patent: 4144562 (1979-03-01), Cooper
patent: 4322815 (1982-03-01), Broughton
patent: 4332010 (1982-05-01), Messina et al.
patent: 4400774 (1983-08-01), Toy
patent: 4464712 (1984-08-01), Fletcher
Allen Jerrold L.
Brinson Gregory D.
Chao Chenyu
Goldsbury Timothy G.
Gunderson Robert O.
Dugas Edward
Eng David Y.
Gonzalez Floyd A.
Hawk Jr. Wilbert
NCR Corporation
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