Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2000-12-18
2002-10-08
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S143000
Reexamination Certificate
active
06462688
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates generally to signal processing and signal waveshaping. More particularly, the present invention relates to signal processing and signal waveshaping of digital-to-analog converters.
BACKGROUND AND RELATED ART
Digital-to-analog conversion involves the process of converting digital codes into a continuous range of analog signal levels (voltage or current), for example, as discussed in Chapter 31, “D/A and A/D Converters” of The Electrical Engineering Handbook, ed. Richard C. Dorf, CRC Press 1993, the contents of which are hereby incorporated by reference. A digital-to-analog converter (hereinafter a DAC) is generally an electronic circuit that receives an n-bit codeword from an interface and generates an analog voltage or current that is proportional to the codeword.
One example of a DAC is discussed in U.S. Pat. No. 5,663,728, entitled A Digital-To-Analog Converter (DAC) and Method that set Waveform Rise and Fall Times to Produce an Analog Waveform that Approximates a Piecewise Linear Waveform to Reduce Spectral Distortion, issued on Sep. 2, 1997, the contents of which are hereby incorporated by reference. The DAC of the U.S. Pat. No. 5,663,728 patent employs a waveform shaping circuit to control the rise and fall times of each component waveform so that the analog waveform rising and falling edges settle to within a desired error bound of a linear output ramp.
U.S. Pat. No. 5,936,450, entitled A Waveshaping Circuit Using Digitally Controlled Weighted Current Summing, issued on Aug. 10, 1999, the contents of which are hereby incorporated by reference, discloses a waveshaping circuit. The waveshaping circuit of the U.S. Pat. No. 5,936,450 patent includes a controller and a current summing circuit controlled by the controller. The current summing circuitry selectively sinks combinations of component currents in response to a sequence of control signal sets to generate an output current signal having a desired waveform.
Many DACs attempt to generate desired signal waveform in response to a digital signal. For the purposes of this discussion, a signal output may include the output of a DAC and/or the output of one or more signal components within a DAC. For example, a signal component may correspond to an individual bit of a codeword. One conventional method generates a signal output with a slew rate controlled current source, as shown in FIG.
1
. The voltage V measured across a resistor R is shown in FIG.
2
. The waveform V includes sharp transition areas (e.g., corners)
1
,
2
and
3
, which may introduce electromagnetic interference. Such interference may inhibit accurate signal processing.
Another circuit which generates an output signal employs a current mirror
10
having an RC filter, as illustrated in
FIG. 3. A
current source I drives the current mirror
10
. Current mirror
10
includes a first transistor
11
and a second transistor
12
. Transistors
11
and
12
are preferably CMOS transistors. The first transistor
11
includes gate-to-drain feedback, and is coupled to transistors
12
through the RC filter. The RC filter limits rise and fall times of the input signal I. However, the R and C components are typically process and/or temperature dependent. Such dependence causes variation in the output waveform as shown in FIG.
4
. The dashed lines in
FIG. 4
represent arbitrary output responses due to temperature and/or process variation. A stable output signal is difficult to obtain with such a circuit.
FIG. 5
depicts a D/A circuit employing a DAC
32
, a low pass filter
34
, a voltage buffer
36
, a transistor
38
,and a resistor
39
. Each level of a multilevel input signal is provided to DAC
32
for conversion to an analog signal. The LPF
34
then determines the rise time of the output of the DAC
32
, and the output is passed to voltage buffer
36
. This construction presents two problems. First, the R and C values of LPF
34
will vary with temperature and process variations, and the output signal will have a poor waveshape where the rise times are not constant. Second, since all input current is passed through the same DAC, and since bandwidth is a function of current level, each level of the multilevel signal will present a different rise time.
These signal processing problems are not adequately addressed in the art. Accordingly, there is a need for a current source to control an output signal which is independent of temperature and process considerations. There is also a need for a DAC to generate a signal having selectable transition areas (corners). There is a further need of a circuit to generate desirable waveshapes.
SUMMARY OF THE INVENTION
The present invention addresses these signal processing problems by providing a circuit to generate a desired output signal. The present invention also provides a DAC for converting a digital signal into an analog signal with a desirable waveshape.
According to a first aspect of the present invention, a current source includes N current sources configured in a parallel arrangement, wherein N is at least two. Each of the N current sources includes a respective control input. The current source includes M delay elements, with an mth one of the M delay elements including an input in communication with an m−1th one of the M delay elements. M is equal to N−1, and an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources.
According to another aspect of the present invention, an apparatus includes N current sources configured in a parallel arrangement, wherein N is at least two. Each of the N current sources includes a respective control input and a respective biasing input. The apparatus also includes a biasing generator in communication with each of the biasing inputs of the N current sources, an apparatus input in communication with the control input of a first one of the N current sources, and M delay elements, with an mth one of the M delay elements including an input in communication with an m−1th one of the M delay elements. M is equal to N−1, and an output of the mth one of the M delay elements is arranged in communication with the control input of an m+1th one of the N current sources. The first one of the M delay elements is in communication with the apparatus input.
A method of supplying current is provided according to still another aspect of the present invention. The method includes the steps of: (i) arranging first through n current sources in a parallel arrangement, where n comprises the total number of current sources, and wherein the first current source supplies a first current and the second through n current source respectively supplies second through n currents; and (ii) delaying the second through n currents each with respect the first current.
These and other objects, features and advantages will be apparent from the following description of the preferred embodiments of the present invention.
REFERENCES:
patent: 3543009 (1970-11-01), Voelcker, Jr.
patent: 4947171 (1990-08-01), Pfiefer et al.
patent: 5625357 (1997-04-01), Cabler
patent: 5663728 (1997-09-01), Essenwanger
patent: 5936450 (1999-08-01), Unger
patent: 6172634 (2001-01-01), Leonowich et al.
patent: RE37619 (2002-04-01), Mercer et al.
patent: 2001/0050585 (2001-12-01), Carr
“Gigabit Ethernet 1000BASE-T”, Gigabit Ethernet Alliance, copyright 1997.
Janofsky Eric B.
Katten Muchin Zavis & Rosenman
Marvell International Ltd.
Williams Howard L.
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