Direct digital synthesizer with output signal jitter reduction

Details Direct digital synthesizer with output signal jitter reduction Direct digital synthesizer with output signal jitter reduction

2006-09-05

2006-09-05

Bayard, Emmanuel (Department: 2611)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S101000, C708S250000, C708S103000, C708S008000, C708S271000, C327S106000, C327S105000, C327S161000, C327S107000, C375S362000, C375S376000

Reexamination Certificate

active

07103622

ABSTRACT:
A method and apparatus for reducing unwanted harmonics in direct digital synthesizer (DDS) output. The method comprises the steps of providing a set of k phase-shifted clock signals, examining, in succession, each DDS accumulator state, and determining whether the DDS accumulator state has a defined transition-state. For each DDS accumulator state having a defined transition-state, an interpolation is performed based upon the value of the preceding DDS accumulator state, an element of the set of phase-shifted clock signals is selected based upon the interpolation, and the most significant bit (MSB) is repositioned using the selected element of the phase-shifted clock signals. The apparatus comprises means for providing a set of k phase-shifted clock signals, means for examining, in succession, each DDS accumulator state, and means for determining whether the DDS accumulator state has a defined transition-state. The apparatus further includes means for performing an interpolation, for each DDS accumulator state having a defined transition-state, based upon the value of the preceding DDS accumulator state, means for selecting an element of the set of phase-shifted clock signals based upon the interpolation, and means for repositioning the MSB using the selected element of the phase-shifted clock signals.

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