Direct digital synthesizer phase locked loop

Details Direct digital synthesizer phase locked loop Direct digital synthesizer phase locked loop

2002-03-01

2003-12-16

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

06664827

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of communication systems and, in particular, to systems for establishing a timing signal for synchronization of communications.
BACKGROUND
Communications systems generally require that the operation of synchronous transmission elements within the system be coordinated to some timing signal derived from a reference clock signal. The derived timing signal is synchronized, or locked, to the reference clock signal. One well-known clock synchronization technique is the use of a phase locked loop (PLL).
A PLL is a frequency-selective circuit generally containing a phase comparator, a low-pass filter, and an oscillator coupled in a feedback arrangement. When an input or reference clock signal is applied to the PLL, the phase comparator compares the phase of the reference clock signal with the phase of the oscillator output signal and generates an error signal that is related to the phase relationship between the two signals. This error signal is filtered, amplified, and applied to the oscillator, thus driving the frequency of the oscillator output signal in a direction to more closely align its phase to that of the reference clock signal. When the oscillator output frequency is sufficiently close to the reference frequency, the feedback nature of the PLL causes the oscillator output to lock to the reference clock signal frequency, with the exception of some finite phase difference. The point is called the “zero phase error.” While the phases may not be aligned, their frequencies are matched such that the amount of phase difference remains substantially constant. The self-correcting nature of the PLL thus allows the system to track the frequency changes of the reference clock signal once it is locked. A frequency divider is often inserted in the feedback loop when the desired output frequency of the oscillator is some multiple of the reference clock signal frequency.
FIG. 1
is a block diagram of a typical PLL
100
. The PLL
100
includes a phase comparator
110
having a first input for the reference clock signal and a second input for the feedback signal. The output of the phase comparator
110
is coupled to the input of a loop filter
120
. The output of the loop filter
120
is coupled to the input of an oscillator
130
for providing the control signal to the oscillator
130
. The oscillator
130
is often a voltage-controlled oscillator (VCO) or a digitally-controlled or numerically-controlled oscillator (NCO). An NCO generally includes a fixed-frequency oscillator and a synthesizer for providing a scaled output signal derived from a reference frequency of the fixed-frequency oscillator. The output of the oscillator
130
is fed back to the second input of the phase comparator
110
through a frequency divider
140
.
Crystal oscillators are generally used in precision PLLs. These oscillators are preferred due to their high accuracy. Such oscillators are capable of maintaining a frequency within 1 ppm of the desired frequency. However, crystal oscillators may be prone to long-term drift.
In communications systems, the timing signal must be maintained, even if the reference clock signal is lost, in order to avoid loss of transmission data. A holdover signal may be applied to the oscillator as a control signal in the event the PLL goes open-loop, i.e., the PLL loses its reference clock signal. The holdover signal is the expected control signal necessary to produce the desired frequency of the timing signal. Due to the possibility of long-term drift, however, this holdover signal may not produce the expected frequency. To compensate, the holdover signal may represent the most recent control signal prior to losing the reference clock. However, the failure causing the loss of the reference clock may also introduce significant noise prior to the loss, thus producing an inappropriate holdover signal.
Another problem encountered by PLLs is a step change in the incoming reference clock signal. A typical PLL will attempt to track a phase or frequency step change in the reference clock signal, causing a disruption in the frequency output of the PLL until the signals are once again locked.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative systems capable of establishing a communications timing signal.
SUMMARY
The above-mentioned problems with communications systems and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The various embodiments of the invention make use of phase locked loops adapted to filter and store data indicative of the control signal applied to an oscillator. Such phase locked loops permit suppression of tracking in the event of a step change in the phase difference between the reference clock signal and the feedback signal in the phase locked loop. Such phase locked loops further facilitate compensation for drift of the oscillator. Phase locked loops of the various embodiments are suitable for use in timing circuits of communications systems.
For one embodiment, the invention provides a phase locked loop. The phase locked loop includes a digital phase comparator having a first input for receiving a reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal; a digital loop filter having an input for receiving the error signal and an output for providing a control signal; a numerically-controlled oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal; a processor coupled to the digital phase comparator; and a machine-readable medium coupled to the processor. The machine-readable medium has instructions stored thereon adapted to cause the processor to monitor the digital phase comparator, to detect a step change in a phase relationship between the reference clock signal and the feedback signal, and to recenter the digital phase comparator if a step change is detected.
For another embodiment, the invention provides a phase locked loop. The phase locked loop includes a digital phase comparator having a first input for receiving a reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal; a digital loop filter having an input for receiving the error signal and an output for providing a control signal; a numerically-controlled oscillator having a frequency synthesizer and a fixed frequency source, wherein the frequency synthesizer has a first input for receiving the control signal, a second input for receiving a reference frequency, and an output for providing a timing signal in response to the control signal and the reference frequency; a low-pass filter having an input for receiving the control signal; a processor coupled to the low-pass filter; and a machine-readable medium coupled to the processor, wherein the machine-readable medium has instructions stored thereon adapted to cause the processor to sample and store data from the low-pass filter indicative of an average control signal, to compare the average control signal to a threshold limit, and to trim the oscillator if the average control signal is outside the threshold limit.
For yet another embodiment, the invention provides a method of generating a timing signal. The method includes generating an error signal indicative of a phase relationship between a reference clock signal and a feedback signal using a phase comparator; filtering the error signal to produce a control signal for a frequency synthesizer; generating the timing signal in response to the control signal; deriving the feedback signal from the timing signal; monitoring the phase comparator for a step change in the phase difference between the reference clock signal and the feedback signal; and recentering the phase

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