Direct digital synthesizer

Details Direct digital synthesizer Direct digital synthesizer

2000-02-02

2004-06-08

Ingberg, Todd (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S270000, C327S105000

Reexamination Certificate

active

06748407

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a direct digital synthesizer for use in communication equipment, and more particularly to a direct digital synthesizer for supplying signals of a prescribed frequency in accordance with an entered reference clock and frequency data that are set.
2. Description of Related Art
A direct digital synthesizer (DDS) conventionally used in communication equipment is usually provided with a phase accumulator. This phase accumulator consists of an adder. This adder receives frequency data at one of its inputs and its own output at the other, adds them in synchronism with an external clock, and successively supplies the results of addition as the output of the phase accumulator.
The output value of this phase accumulator is entered into a phase-amplitude converter to be converted into amplitude data of DDS output signals. More specifically, many of such phase-amplitude converters convert the computation output of a phase accumulator into amplitude data of a sine waveform. Next, these amplitude data are converted by a D/A converter into analog signals to obtain DDS output signals.
In designing a DDS, first the frequency of a reference clock and the number of bits computed by the phase accumulator are determined according to the step of frequency required for the output signal.
Next, with this reference clock frequency being used as the sampling rate, the number of input bits for the D/A converter is determined according to the precision requirement of output signals, and the number of output bits for the phase-amplitude converter is determined to match the number of input bits for the D/A converter. Finally the number of bits to be entered into the phase-amplitude converter out of the computation result of the phase accumulator is determined.
Incidentally, D/A converters for use in a DDS are usually expensive. Therefore, a device with the minimum required number of input bits is selected.
On the other hand, the number of bits computable by the phase accumulator is determined by the frequency step required for output signals. For this reason, the smaller the output frequency step, the greater the number of bits required.
Accordingly, in many cases, the number of bits computable by the phase accumulator is substantially greater than the number of output bits of the phase-amplitude converter (equal to the number of input bits of the D/A converter). Therefore, the designer arranges his or her design so that only the more significant bits out of the computation result of the phase accumulator be entered into the phase-amplitude converter without entering some of the less significant bits, because entering a greater number of bits into the phase-amplitude converter, greater beyond a certain limit, than that of output bits would require an extremely large scale phase-amplitude converter, which inevitably is expensive.
On the other hand, the value represented by the less significant bits not entered into the phase-amplitude converter out of the computation result of the phase accumulator constitutes the rounding error of the input data for the phase-amplitude converter. However, as this rounding error is used every time the phase accumulator repeats its computation, a carry occurs on the more significant bits periodically.
Since input data for the phase-amplitude converter contain such carries, the sine waveform of DDS output signals suffers phase jumps at the frequency of carry occurrence, and spurious signals arise in the spectrum of DDS output signals. The occurrence of such spurious signals will be explained in more detail below. A spurious signal arises as a consequence of either one of the following two circumstances.
[1] A phase jump in an output signal resulting from periodic carries to more significant positions of the result of addition of less significant bits not entered into the phase-amplitude converter out of the output bits of the phase accumulator, and a spurious signal attributable to it:
For the sake of simplicity of explanation, the output of the phase accumulator is divided into more significant m bits and less significant n bits (m and n are natural numbers; the same applies hereinafter), m being 4 and n, also 4.
It is supposed that the more significant m bits are entered into the phase-amplitude converter, but the less significant n bits are not.
It is further supposed that both the more significant m and the less significant n bits be connected to one of the inputs of the phase accumulator, frequency set data S are entered into the other input, and the addition is repeated in accordance with a reference clock.
Further explanation will be given below with reference to specific actions.
The initial value P
0
of the computation result of the phase accumulator is supposed to be:
P
0
=0000, 0000(
B
)  (1)
“(B)” in Equation (1) indicates binary notation, and “,” represents the boundary between the more significant m and less significant n bits.
Now the frequency set data being represented by S
1
, the following being set:
S
1
=0100, 0000(
B
)  (2)
and the result of four rounds of addition by the phase accumulator being represented by P
1
:
P
1
=0000, 0000(
B
)  (3)
As the addition is further repeated, the phase accumulator repeats supplying the same computation result in periods of four rounds of addition each, and the DDS output signals then are stable signals, free from spurious signals.
However, if the frequency set data are represented by S
2
, the following is set:
S
2
=0100,0001(
B
)  (4)
and the result of four rounds of addition by the phase accumulator is represented by P
2
:
P
2
=0000, 0100(
B
)  (5)
As the more significant m bits of P
2
here is 0000(B), the same value as P
1
of (3) is entered into the phase-amplitude converter, but the less significant n bits involve a rounding error for 0100(B).
This rounding error, if the phase accumulator further repeats addition, gives rise to a carry to the more significant m bits in the 16th round. The addition result then being represented by P
3
:
P
3
=0001, 0000(
B
)  (6)
will hold, the more significant m bits being different from P
1
. This invites a phase jump in the DDS output signals.
Since a carry from the less significant n bits to the more significant m bits occurs every 16th round of addition by the phase accumulator, the DSS output signals suffer a phase jump at the same frequency. This invites a spurious signal of a frequency corresponding to the interval of phase jumps in the spectrum of DDS output signals. The frequency fs of such spurious signals can be generally expressed in the following equation.
fs
1
={mod(
S
/2
n
)/2
n
}·f
clock
  (7)
In the foregoing equation, mod(A/B) represents the remainder of the division of A by B.
[2] A phase jump in output signals attributable to the remainder at the time of an accumulator overflow, and a spurious signal attributable to it:
A DDS output signals suffers the occurrence of a phase jump and a spurious signal, besides where the circumstance of [1] described above arises, when remainders at the time of overflowing of the phase accumulator have built up to overflow the accumulator.
For instance, where the value of the frequency set data S is set to be:
S
3
=0100, 0111(
B
)  (8)
if the addition is done four times, the accumulator will be overflowed. The value P
4
of the accumulator then will be:
P
4
=0001, 1100(
B
)  (9)
This remainder will build up, and eventually this accumulated value itself will overflow the accumulator.
For instance, the next overflow will arise when the eighth addition is done, the remainder P
8
then having built up in the accumulator will be:
P
8
=0011, 1000(
B
)  (10)
At the following
11
th addition, the accumulator will be overflow ed. At this time, the accumulator will have a further remainder P
11
:
P
11
=0000, 1101(
B
)  (11)
This r

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