Direct digital synthesizer

Details Direct digital synthesizer Direct digital synthesizer

1998-10-29

2003-03-25

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S272000

Reexamination Certificate

active

06539411

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improved direct digital synthesizer.
2. Description of the Related Art
Direct digital synthesis (DDS) is an electronic circuit technique used to generate periodic waveforms. A direct digital synthesizer generates a stream of digital data which is transformed into an analog waveform with a digital-to-analog converter (DAC). A direct digital synthesizer operates by clocking a binary accumulator (typically greater than or equal to 24 bits) at a high frequency (for example, >100 Mhz).
The accumulator is essentially an adder circuit with one input and one output. At every clock signal, the input value is added to the current output value and the output of the accumulator assumes a new sum. The input, usually referred to as a control word, specifies the magnitude of the count increment. If the control word is 250, the accumulator will count in a 0, 250, 500, 750, 1000 . . . sequence until it rolls over and continues.
A known direct digital synthesizer
1
is shown in
FIG. 1. A
value “N”, which is essentially a variable control word, is loaded into a control register
2
from a microprocessor (&mgr;P)
3
. The control word, with a variable value “N” such as 250 for example, is then input to an accumulator
4
. The accumulator
4
adds a present count value A to a previous count value B, and outputs the combined count or output sum to a lookup table
6
. The lookup table
6
then provides an output to a digital-to-analog converter (DAC)
8
. The operation of this direct digital synthesizer
1
is described as follows.
The lookup table
6
, which receives an accumulated output consisting of the count value A and the previous count value B, stores values representing amplitudes of the synthesized signal, which can be a sine wave signal, for example. As the accumulator
4
steps through its counting range, the lookup table
6
outputs a digital representation of a sine wave, for example or other waveform shape. The output from lookup table
6
is then input to DAC
8
. The DAC
8
outputs an analog waveform at a frequency established by the magnitude of the control word divided by the maximum count of accumulator
4
(for example 2
24
for a 24-bit counter, multiplied by the clock frequency). Accordingly, if the control word “N” has a value of 250, and the clock rate of 60 MHz clocks a 24-bit accumulator
4
, the frequency of the output signal will be 894.1 Hz. A control word “N” of 251, produces an output signal at a frequency of 897.6 Hz. Thus, from one high-frequency clock, a direct digital synthesizer
1
generates periodic analog signals of a wide range of precisely controlled frequencies.
Creating an efficient DDS requires balancing conflicting requirements of circuit speed, complexity and function. An accumulator-based DDS provides a general purpose function because it can add any number to its current input. This generality makes the circuit slow and complex. In the past, to raise the frequency of operation in an attempt to extend the range of potential applications of the DDS
1
, either pipelined adder circuits were used, or more costly digital logic processes such as circuits based on emitter-coupled logic. Although pipelined adder circuits increased the speed by which the control word was added to the current count, the circuit was made even more complex, which increased cost.
In an effort to illustrate the digital logic equations required to implement such a general purpose accumulator, such as accumulator
4
, a Cypress Inc. WARP2 VHDL (very high speed integrated circuit Hardware Descriptor Language) compiler, Version 4.2, was used. This generated the necessary logic equations for a 24-bit accumulator which added a 24-bit input value N[
23
:
0
] to a current input D[
23
:
0
] on a rising edge of the clock signal. The following code illustrates the VHDL statements necessary to specify a 24-bit accumulator.
library ieee;
use ieee.std_logic_
1164
.all;
use work.std_arith.all;
entity countby_N is port (
clock: in std_logic;
N: in std_logic_vector (
23
downto
0
);
D: buffer std_logic_vector (
23
downto
0
));
end countby_N;
architecture DDS of countby_N is begin
accumulator: process (clock)
begin
if (clock' event and clock=‘1’) then
D<=D+N;
end if;
end process accumulator;
end DDS.
Utilizing the aforementioned code, the VHDL compiler synthesized a 24-bit accumulator. The equations of twenty-four outputs D[
23
:
0
] are shown in Appendix A, attached hereto. The resulting logic, targeted for a Cypress Incorporated Programmable Logic (CIPL) device, contained 128 macrocells and 640 product terms. Macrocells and product terms are common measures of complexity used to characterize complex programmable logic devices. When optimized for fastest circuit speed, 55 of the 128 macrocells were required; 210 of the 640 unique product terms were required; and the maximum clock speed was 52.6 Mhz. When optimized for the smallest circuit area, 55 of the 128 macrocells were required; 165 of the 640 unique product terms were required; and the maximum clock speed was 14.5 Mhz.
Thus, an accumulator-based DDS, even if optimized for speed or size, is still slow and complex. Further, when optimized for speed, it is extremely complex and when optimized for size, it is extremely slow. Accordingly, a better DDS is needed.
SUMMARY OF THE INVENTION
An improved direct digital synthesizer simplifies digital circuitry required by utilizing an adder which counts by a predetermined fixed increment (count by C counter). Such a counter is preferably designed using a non-volatile reconfigurable complex programmable logic device (CPLD) IC. A digital circuit configuration is designed to count only at the required increment loaded into the CPLD. Such a specified increment counter provides for a DDS which operates at a much higher frequency than comparable DDS utilizing a general purpose accumulator.


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patent: 5554987 (1996-09-01), Ooga
patent: 5963607 (1999-10-01), Romano et al.
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JPO Office Action, Synopsis of relevance JP Application 51-105259 Abstract.
Japanese Office Action; Examiner: M. Kobayashi; Patent Application No. 307917/1999; Dec. 11, 2001.
Canadian Office Action, Examiner: Andrew O'Malley; Application No. 2,281,407, Dec. 19, 2001.
“CMOS, 125 MHz Complete DDS Synthesizer”,Analog Devices 9850, 1997; pp. 1-19.

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