Direct digital synthesis with low jitter

Details Direct digital synthesis with low jitter Direct digital synthesis with low jitter

2007-09-11

2007-09-11

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synthesizer

C327S107000, C327S159000

Reexamination Certificate

active

11128774

ABSTRACT:
An FPGA having a programmable frequency output is provided that achieves a (theoretical) M-times reduction in output jitter from a conventional direct digital synthesis (DDS) circuit, by running M accumulator circuits in parallel and combining the outputs in a time-staggered way. I Initially the frequency number N added into the accumulators is varied slightly for each accumulator by multiplying by a number, such as X/16 where X varies from 1 to 16 for each of 16 accumulator circuits. The accumulator circuits are further reconfigured so that the output of a register from a first accumulator provides feedback to the adder input in all of the accumulator circuits. The number of overflowing accumulator registers in a clock cycle will then indicate granularity spatially. To translate spatial granularity to time, a programmable delay circuit is connected to the output of each accumulator register.

REFERENCES:
patent: 4992743 (1991-02-01), Sheffer
patent: 5371765 (1994-12-01), Guilford
patent: 5673212 (1997-09-01), Hansen
patent: 6693468 (2004-02-01), Humphreys et al.

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