Direct digital synthesis using a sine weighted DAC

Details Direct digital synthesis using a sine weighted DAC Direct digital synthesis using a sine weighted DAC

1999-09-21

2001-08-28

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C331S023000

Reexamination Certificate

active

06281823

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to direct digital synthesizers. More particularly, it relates to a direct digital synthesizer having improved spurious performance extending a frequency of operation, reducing chip area, and reducing power consumption, relative to conventional direct digital synthesizer techniques.
2. Background of Related Art
Direct digital synthesizer (DDS) techniques have been used for years in a variety of telecommunications applications, but conventional architectures require high-performance digital-analog converters (DACs) with many bits of resolution and fast settling times. These conventional designs provide adequate spurious performance for use in applications such as local oscillators, generation of frequency shift keying (FSK) or phase shift keying (PSK) modulation waveforms, etc.
For instance, direct digital synthesis (DDS) has had a dramatic impact on the “best approach” to bench-top function generators. Over the last few years, improvements in LSI logic, fast random access memories (RAM), and digital-to-analog converters (DACs) have made DDS the technology of choice for this application.
FIG. 3
shows a block diagram of a conventional direct digital synthesis system including a look-up table memory.
In particular, there are three major components to a conventional sine wave DDS: a phase accumulator
312
, a sine wave look-up table
304
, and a digital-to-analog converter (DAC)
302
.
A numerically controlled oscillator (NCO)
310
is formed by adding a phase increment value
318
to a fed back output from a phase accumulator
312
in an adder
316
. The adder is clocked with an appropriate clock
314
.
The output of the NCO
310
is input as an address to a memory-based look-up table, e.g., a sine-wave look-up table
304
. The value stored in the indexed address in the look-up table
304
is output to a high resolution digital-to-analog converter
302
. The DAC
302
is conventionally of high resolution, e.g., of at least 10-12 bits.
The output of the DAC
302
is smoothed using an appropriate reconstruction filter
306
such as a low pass filter.
In operation, the phase accumulator
312
computes an address for the sine wave look-up table
304
(which is typically stored in memory such as RAM or ROM). The sine wave value output by the lookup table
304
is converted to an analog voltage level by the digital-to-analog converter (DAC)
302
.
To generate a fixed frequency sine wave, a constant value (i.e., the phase increment value
318
) is added to the output of the phase accumulator
312
with each pulse of the clock
314
. If the phase increment value
318
is large, the phase accumulator
312
will step quickly through the sine look-up table
304
, and correspondingly will generate a high frequency sine wave.
One might think that to generate a “clean” sine wave you would need hundreds or thousands of points in each cycle of the sine wave. In fact, you only need about three. Of course, a three step approximation to a sine wave hardly looks like a sine wave, but if the conventional DAC
302
is followed with a good low-pass filter
306
, the high frequency components are removed leaving a clean sine wave.
The frequency resolution of the conventional DDS is determined by the number of bits in the phase accumulator
312
and the clock frequency. A high number of bits provides a very high resolution in the frequency, and thus the general emphasis in conventional DDS systems is for use of a high number of bits to provide high resolution. For instance, a conventional 32-bit phase accumulator would provide a frequency resolution of 1 part in 2
32
(approximately 4.3 billion) relative to the master clock frequency.
The maximum output frequency obtainable from a DDS depends on the master clock frequency which controls the sequential addition of phase increment values to the previously accumulated phase value fed back from the phase accumulator. Theoretically, the maximum frequency output would be limited by the Nyquist criterion to Fclock/
2
. However, in practice, as the Nyquist frequency is approached and the number of samples per cycle of the output waveform decreases the spurious performance degrades to unacceptable levels. Thus conventional DDS devices are frequently used to generate frequencies up to only something on the order of ⅔ of the Nyquist frequency.
Many applications require hopping rapidly between various sine wave frequencies. To allow for agile modulation of the frequency and/or phase of the output signal, it is relatively common to provide for a pair or more of registers which can be pre-loaded with different phase increment values and selectively multiplexed into the phase increment input of the DDS' adder/phase accumulator.
The adder/phase accumulator/sine (or cosine) lookup table functions could also be implemented as a software algorithm running on a fast microprocessor or digital signal processor, but generally such functions are realized in dedicated digital logic in the interest of obtaining the fastest possible operation and thus higher operating frequencies.
The phase accumulator
312
in conventional DDS systems typically includes a rather large number of bits (e.g., 24 to 32) to provide a fine resolution in frequency. However, it is common practice to truncate this value to a smaller and more manageable number of bits, N, by using only the N most significant bits of the output of the phase accumulator
312
in a stage following the phase accumulator
312
, e.g., at the input to the look-up table
304
. Generally, these N most significant bits output by the phase accumulator
312
are used as an address into the look-up table
304
. The look-up table
304
is a sine wave look-up table containing sine wave values in appropriate address locations corresponding to the desired value of the instantaneous phase which has been accumulated. The sine-valued outputs of the look-up table
304
are often further truncated to a resolution of something on the order of 10 or 12 bits, since it is increasingly difficult to produce a linear DAC
302
with both higher resolution and adequate settling time for high frequency operation.
This architecture results in a stepped approximation to a sine wave signal output from the digital-to-analog converter (DAC)
302
, the stepped approximation improving with additional resolution (i.e., bits). However, even though a design may allow for a large number of steps per cycle of the output frequency at low frequencies, as the Nyquist frequency is approached the steps per cycle nevertheless reduces to very few steps per cycle of the output frequency. The result is that the spurious performance of a conventional DDS generally degrades as the output frequency increases towards the Nyquist limit. Thus, the usable output frequency of a conventional DDS is considerably less than its Nyquist frequency.
Moreover, the need for a DDS with high resolution and minimal spurious performance requires the digital-to-analog converter
302
to be capable of resolving a large number of discrete output levels. This drives the need for larger numbers of bits of resolution, which in turn requires a digital-to-analog converter (DAC)
302
with a correspondingly large number of taps in its resistor string. Unfortunately, each additional tap in the DAC
302
increases its parasitic capacitance rapidly and significantly, making it increasingly difficult to achieve the fast settling times necessary to meet today's high frequency operation requirements. Of course, this refers strictly to a resistor string type DAC. Other architectures are possible, e.g., switched capacitors. Nevertheless, in general, as the resolution of the DAC increases, area and power dissipation increase, and speed decreases.
There is thus a need for a direct digital synthesis (DDS) technique and apparatus which has improved spurious performance even at higher frequencies of operation.
SUMMARY OF THE INVENTION
A direct digital synthesizer in accordance with the principles of the present in

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