Direct digital synthesis (DDS) phase locked loop (PLL)...

Details Direct digital synthesis (DDS) phase locked loop (PLL)... Direct digital synthesis (DDS) phase locked loop (PLL)...

2007-07-31

2007-07-31

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S034000, C375S376000, C455S260000, C332S123000, C332S126000, C332S127000

Reexamination Certificate

active

11136968

ABSTRACT:
The phase locked loop (PLL) frequency synthesizer includes a phase detector receiving a reference signal, a controlled oscillator (e.g. a voltage controlled oscillator) connected to the phase detector and generating a synthesized frequency output signal based upon the reference signal, a mixer (e.g. an in-phase and quadrature-phase (IQ) modulator) connected to the controlled oscillator, a divider connected between the mixer and the phase detector, and a signal source driving the mixer. The frequency synthesizer and method have narrow frequency steps (e.g. as low as fractions of a Hertz) while using a relatively high reference frequency to maintain low phase noise. Furthermore, the fine frequency tuning resolution is achieved while also reducing output spurs and using a relatively simple topology.

REFERENCES:
patent: 5847615 (1998-12-01), Roth
patent: 5986512 (1999-11-01), Eriksson
patent: 6384772 (2002-05-01), Bradley
patent: 6441690 (2002-08-01), Savelli et al.
patent: 6587511 (2003-07-01), Barak et al.
patent: 2004/0121744 (2004-06-01), Wannenmacher

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