Direct digital frequency multiplier

Details Direct digital frequency multiplier Direct digital frequency multiplier

1992-03-30

1993-10-26

Sikes, William L.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

377 48, H03K 378

Patent

active

052573010

ABSTRACT:
An improved direct digital frequency multiplier that multiplies input frequencies by a factor equal to the number of comparators in the circuit divided by two. The circuit includes a sensing stage, a ramping stage, a storage stage, a comparison stage and a logic stage. A signal containing the frequency to be multiplied is input to the sensing stage, which determines the frequency of the signal and outputs timing signals to the rest of the circuit. Coinciding with the period of the input signal, ramping voltages are generated, whose peak voltages are sampled and held for a specific time. The linearly ramping voltages are compared with the peak voltages and the comparison stage outputs voltage spikes to the logic stage. The logic stage combines the outputs from the comparison stage, and outputs a square wave signal possessing the appropriate multiplied frequency.

REFERENCES:
patent: 4063070 (1977-12-01), Delarue et al.
patent: 4570089 (1986-02-01), Nagano
patent: 4691170 (1987-09-01), Riley
patent: 4773031 (1988-09-01), Tobin
patent: 4870684 (1989-09-01), Arai et al.
patent: 4956797 (1990-09-01), Berard

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