Direct deposit thin film single/multi chip module

Details Direct deposit thin film single/multi chip module Direct deposit thin film single/multi chip module

1999-10-27

2001-07-17

Gulakowski, Randy (Department: 1746)

Etching a substrate: processes

Forming or treating electrical conductor article

C427S096400

Reexamination Certificate

active

06261467

ABSTRACT:

DESCRIPTION
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to Integrated circuit (IC) chip packaging and, more particularly, to high signal density IC chip packaging for packaging single or multiple ICs inca single module and the method of manufacture thereof.
2. Background Description
Performance and signal density demands are forcing Single chip modules (SCMs) and, especially, multi-chip modules (MCMs) to become more and more complex. Ceramic module signal density is being increased by increasing the number of ceramic wiring layers (with one wiring or power layer on each ceramic layer). However, increasing signal density, increases signal load capacitance and impairs chip performance.
Thin film (TF) wiring layers on ceramic substrates have increased module wiring density and improved signal transmission characteristics, while dramatically reducing the number of ceramic layers. However, these modules require reference voltage layers for noise reduction and, when required, for impedance matching.
Typically, these ceramic modules include at least two TF layers for defining capture pads, a ground plane layer, and wiring layer. Unfortunately, these TF processes adapted for making such a module are very expensive because they require a planar ceramic substrate surface.
Thus, new cost effective methods are needed to reduce the TF ceramic fabrication costs.
SUMMARY OF THE INVENTION
It is a purpose of the invention to improve the performance of densely wired multi-chip and single chip modules.
It is another purpose of the present invention to reduce the cost for multi chip and single chip ceramic modules that include thin film wiring layers.
The present invention is a high performance module and method of fabricating the module. The module may be a single chip module (SCM) or a multi-chip module (MCM). The preferred module structure includes both thick and thin film layers. In one preferred embodiment, metal layers on top of ceramic substrates are directly deposited by thick film or ceramic processes. Then, redistribution layers are defined by thin film processes.
The thin film (TF) layers are formed directly on a layered ceramic base. A first wiring layer is formed on or embedded in a top surface of the layered ceramic base. A first dielectric layer of a polyimide or other organic material, or, is formed on top of the first wiring layer. Alternatively, the first dielectric layer may be an inorganic material different than the ceramic material. The dielectric layer, preferably, is spun on or sprayed on and baked. Alternatively, the dielectric layer may be laminated to the ceramic base; or, an inorganic layer may be vapor deposited using plasma enhanced chemical vapor deposition (PECVD) or, by evaporation or sputtering. Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. Then, a passivation layer, or second dielectric layer, is formed on the second wiring layer. At least one mounting location suitable for mounting an electronic component (e.g., IC chips and/or capacitors) is formed in the second dielectric layer. Pins, ball grid array, land grid array or column grid array connections may be attached to the bottom layer of the ceramic base.


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