Direct coupled FET logic with super buffer output stage

Details Direct coupled FET logic with super buffer output stage Direct coupled FET logic with super buffer output stage

1985-04-25

1987-12-29

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307450, 307460, 307574, 307581, H03K 19017, H03K 1716, H03K 19094, H03K 1912

Patent

active

047163119

ABSTRACT:
An integrated logic circuit comprises a direct coupled FET logic input stage and a super buffer logic output stage. The input stage comprises a depletion-mode FET having its drain connected to a first reference potential level and having its gate and source connected together, and a first enhancement mode FET structure having its drain connected to the source of the depletion-mode FET, its source connected to a second, lower reference potential level and having at least one gate connected to receive an input logical signal. The super buffer logic output stage comprises a second enhancement mode FET structure that is essentially identical to the first enhancement mode FET structure, the source of the second enhancement mode FET structure being connected to the second reference potential level and the gate of the second enhancement mode FET structure being connected to the gate of the first enhancement mode FET structure. The output stage also comprises a controllable current source connected between the source of the depletion-mode FET and the drain of the second enhancement mode FET structure, for providing drain current to the second enhancement mode FET structure when the potential of the drain of the first enhancement mode FET structure exceeds a predetermined level, and depriving the second enhancement mode FET structure of drain current when the drain of the first enhancement mode FET structure is below the predetermined potential level.

REFERENCES:
patent: 4443715 (1984-04-01), Fox
patent: 4491747 (1985-01-01), Shimizu
patent: 4558235 (1985-12-01), White et al.
Y. Ikawa et al., "A 1K-Gate GaAs Array", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, Oct. 1984, pp. 721-727.
H. Nakamura et al., "A 390ps 1000-Gate Array Using GaAs Super-Buffer FET logic" ISSCC Digest of Technical Papers of 1985 IEEE International Solid-State Circuits Conference, Feb. 1985, pp. 204 and 205.

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