Direct conversion receiver for frequency-shift keying...

Details Direct conversion receiver for frequency-shift keying... Direct conversion receiver for frequency-shift keying...

1999-12-20

2003-05-13

Chin, Stephen (Department: 2634)

Pulse or digital communications

Receivers

Angle modulation

C375S331000

Reexamination Certificate

active

06563887

ABSTRACT:

The present invention concerns the technical field of receivers able to demodulate electric signals and, more precisely, direct conversion receivers for frequency-shift keying (FSK) modulated signals.
With reference to
FIG. 1
of the present description, European Patent No. 0,405,676 discloses a receiver
1
including an antenna
2
, direct conversion means
3
, two limiting amplifiers
28
and
30
, demodulation means
5
and a bistable memory
6
connected in series.
Antenna
2
receives a frequency-shift modulated signal S and supplies this signal. In the present description, it will be recalled that FSK modulation is a modulation allowing the supply of a signal at a frequency equal to a value fp+&Dgr;f
1
to transmit one of the two states of the signal, and at another value fp−&Dgr;f
1
to transmit the other state, the references fp and &Dgr;f
1
respectively designating a nominal carrier frequency and a frequency shift. For a data rate equal to 512 bits/s, the frequencies fp and &Dgr;f
1
have the respective values 400 MHz and 4.5 kHz.
Conversion means
3
includes two mixers
12
and
14
, a local oscillator
16
, a 90° phase shifter and two low-pass filters
20
and
22
. Oscillator
16
provides a frequency fL which is ideally equal to carrier frequency fp. Mixer
12
(
14
respectively) includes a first input terminal for receiving signal S, a second input terminal for receiving frequency fL, and an output terminal connected to filter
20
(
22
respectively). Moreover, mixer
14
is connected to oscillator
16
via phase shifter
18
. As a result of this arrangement, if the frequency of signal S equals fp+&Dgr;f
1
, the frequencies provided by mixers
12
and
14
respectively equal +&Dgr;f
1
and +&Dgr;f
1
−&pgr;/2 and, if the frequency of signal S equals fp−&Dgr;f
1
, the frequencies provided by mixers
12
and
14
respectively equal −&Dgr;f
1
and −&Dgr;f
1
−&pgr;/2. Filter
20
(
22
respectively) can receive the frequency provided by mixer
12
(
14
respectively) and, in response, provide a signal I (respectively a signal Q). It will be recalled that signals I and Q represent the real and imaginary parts of a complex signal having a negative frequency (in this case −&Dgr;f
1
) or a positive frequency (in this case +&Dgr;f
1
).
FIG. 2
of the present description shows two timing charts
24
and
26
illustrating signals I and Q, respectively. As
FIG. 2
shows, signals I and Q are analog signals having substantially sinusoidal wave shapes in phase quadrature. The presence of a phase change of signal Q will be noted, as illustrated by timing chart
26
.
With reference once more to
FIG. 1
, limiting amplifiers
28
and
30
can receive signals I and Q and, in response, provide signals I
1
and Q
1
respectively. It will be recalled that a limiting amplifier receives an input signal, and provides an output signal whose amplitude does not increase in practice beyond a determined amplitude of the input signal.
FIG. 3A
of the present description shows two timing charts
32
and
34
illustrating signals I
1
and Q
1
respectively. As
FIG. 3A
shows, signals I
1
and Q
1
are digital signals having wave shapes which are offset with respect to each other and rectangular, the amplitudes of signals I
1
and Q
1
equalling −1 or +1.
FIG. 3B
shows a curve
80
illustrating the relationship between the instantaneous values I
1
(t) and Q
1
(t) of signals I
1
and Q
1
at an instant t. As
FIG. 3B
shows, curve
80
has a rectangular shape wherein the peaks are formed by four points A to D. It will be noted that a temporal evolution of these signals translates into a path along this curve, so that, when signal Vout equals 0 (1 respectively), signals I
1
and Q
1
are represented in succession by points A, B, C, D, A . . . (respectively A, D, C, B, A . . . ), i.e. a path along the trigonometric direction (respectively the opposite direction to the trigonometric direction).
With reference once again to
FIG. 1
, demodulation means
5
include a differentiator circuit
40
(
42
respectively), a multiplier
36
(
38
respectively) and a subtractor
39
connected in series.
Multiplier
36
(
38
respectively) includes a first input terminal for receiving signal Q
1
(I
1
respectively) and a second input terminal for receiving signal I
1
(Q
1
respectively), via differentiator circuit
40
(
42
respectively). Multiplier
36
(
38
respectively) is arranged for providing signal X
1
(Y
1
respectively).
FIG. 4
of the present description shows two timing charts
44
and
46
illustrating signals X
1
and Y
1
respectively. As
FIG. 4
shows, signal X
1
contains first pulses, and signal Y
1
contains second pulses offset with respect to the first pulses. Subtractor
39
includes a first input terminal for receiving signal X
1
and a second input terminal for receiving signal Y
1
. Subtractor
39
is arranged to provide a signal X
1
-Y
1
equal to the difference between signals X
1
and Y
1
.
FIG. 5
of the present description shows a timing chart
48
illustrating signal X
1
-Y
1
. As
FIG. 5
shows, signal X
1
-Y
1
contains the pulses resulting from the difference between signals X
1
and Y
1
. It will be noted that, prior to the phase change of signal Q, signal X
1
-Y
1
contains negative pulses and that this phase change causes positive pulses to be supplied.
Bistable memory
6
includes an input terminal for receiving signal X
1
-Y
1
, and an output terminal for providing a signal Vout in response.
FIG. 6
of the present description shows a timing chart
50
illustrating signal Vout. As
FIG. 6
shows, signal Vout is equal to a level <<0>> or to a level <<1>>. It will be noted that, as soon as a positive pulse appears on signal X
1
-Y
1
, signal Vout switches from level <<0>> to level <<1>>, and remains at this level, independently of the subsequent frequency difference between signals X
1
and Y
1
.
The operation of receiver
1
will now be briefly described with reference to
FIGS. 1
to
6
cited above.
Up to an instant t
01
, signals I
1
and Q
1
are periodic of period T, signal I
1
being in advance of signal Q
1
, so that signal Vout equals 0. Signals I
1
and Q
1
are represented in succession by points A, B, C, D, A . . . Thus, at instant t
01
, signal Q
1
becomes equal to 1. At an instant t
1
subsequent to instant t
01
, and prior to instant t
01
+T/2, a new data item is present in signal Q
1
, so that the timing of signals I
1
and Q
1
is reversed after instant t
01
+T/2 (i.e. signals I
1
and Q
1
are represented in succession by points B, A, D, C, B . . . ). It will be noted that the switching of signal Vout occurs during the following switching of signal I
1
to level “−1”, i.e. at an instant t
3
. In other words, there is a time delay between the instant when the data is contained in signal Q (i.e. instant t
1
) and the instant when the data is contained in signal Vout (i.e. instant t
3
). It will also be noted that this time delay is comprised between T/2 and T, which requires a high &Dgr;f/D ratio, the reference &Dgr;f designating the frequency shift (equal in this case to Df
1
) and the reference D designating the bit rate. Thus one drawback of receiver
1
is that there is a high &Dgr;f/D ratio: one bit is typically provided every four periods.
In order to overcome this drawback, there exist in the state of the art FSK modulated signal receivers which perform demodulation directly from the analog signals I and Q provided by the conversion means.
With reference to
FIG. 7
of the present description, U.S. Pat. No. 5,640,428 discloses a receiver
90
including an antenna
2
, conversion means
3
, demodulation means
92
and a low-pass filter
94
. It will be noted that the elements in
FIG. 7
which are similar to those described in relation to
FIG. 1
have been designated by the same references. As
FIG. 7
shows, demodulation means
92
include four mixers
96
to
99
, two holding circuits
100
and

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