Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
1999-06-14
2001-05-22
Tse, Young T. (Department: 2734)
Pulse or digital communications
Receivers
Angle modulation
C375S332000, C329S300000, C329S304000, C455S323000
Reexamination Certificate
active
06236690
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a direct-conversion receiver for a digital-modulation radio signal such as a frequency shift keyed (FSK) signal.
2. Description of the Prior Art
Paging systems of a mobile radio communications network are used for one-way signaling to small receivers (pagers) carried out by individuals. This paging function can signal an individual selectively to take some prearranged action, e.g., call the office, or can deliver a short message. In some of paging systems, a transmitter of a base station can communicate with pagers via digital-modulation radio signals such as frequency shift keyed (FSK) signals.
Direct-conversion receivers can be used as pagers containing FSK demodulators. According to some of the signal transmission standards for a paging system, a base station periodically transmits a digital-modulation radio signal a predetermined number of times, for example, three times. Thus, a pager generally receives a digital-modulation signal the predetermined number of times. The pager selects and uses only one of the first received signal to the last received signal, and disregards the other signals.
U.S. Pat. No. 5,402,449 discloses sample and hold circuits which periodically sample I and Q signals in response to a system clock outputted from a clock signal generator. In U.S. Pat. No. 5,402,449, the sample and hold circuits are successively followed by analog-to-digital converters, a ROM, and a decoder. The decoder includes a latch for periodically sampling and holding a decoding result in response to a data clock. U.S. Pat. No. 5,402,449 does not disclose deciding a logic state of the decoding result at a timing determined by a clock signal which is delayed from a center-symbol clock signal by a specified time. U.S. Pat. No. 5,402,449 does not disclose deciding a logic state of the decoding result at a timing which depends on a frequency error between a local oscillator signal and a received signal.
U.S. Pat. No. 5,086,437 discloses a frequency detector for demodulating a pair of I and Q signals into a digital baseband signal. The frequency detector is followed by a digital data detector which generates a data signal from the digital baseband signal. U.S. Pat. No. 5,086,437 does not disclose deciding a logic state of the data signal (the detection result) at a timing determined by a clock signal which is delayed from a center-symbol clock signal by a specified time. U.S. Pat. No. 5,086,437 does not disclose deciding a logic state of the data signal (the detection result) at a timing which depends on a frequency error between a local oscillator signal and a received signal.
SUMMARY OF THE INVENTION
It is an object of this invention to provide an improved direct-conversion receiver for a digital-modulation signal.
A first aspect of this invention provides a direct-conversion receiver comprising a direct-conversion demodulator; first means for detecting a strength of a received signal; a clock signal generator for generating a clock signal in response to a reception start signal, the clock signal having a frequency corresponding to a symbol rate or higher; second means for sampling an output signal of the demodulator at a timing determined by the clock signal; third means for sampling an output signal of the first means at a timing determined by the clock signal; fourth means for storing “n” output signals of the second means which relate to a signal periodically transmitted from a transmitting station “n” times, wherein “n” denotes a natural number equal to 2 or greater; fifth means for storing “n” output signals of the third means which correspond in timing to the “n” output signals of the second means; sixth means for reading out signals from the fourth means and reading out signals from the fifth means, and for weighing the signals read out from the fourth means in response to the signals read out from the fifth means; and seventh means for combining output signals of the sixth means.
A second aspect of this invention provides a direct-conversion receiver comprising a direct-conversion demodulator; first means for sampling an output signal of the demodulator; second means for storing “n” output signals of the first means which relate to a signal periodically transmitted from a transmitting station “n” times, wherein “n” denotes a natural number equal to 2 or greater; and third means for reading out signals from the second means, and for combining the signals read out from the second means.
A third aspect of this invention provides a direct-conversion receiver comprising a direct-conversion demodulator; first means for detecting a strength of a received signal; second means for sampling an output signal of the demodulator; third means for sampling an output signal of the first means; fourth means for storing “n” output signals of the second means which relate to a signal periodically transmitted from a transmitting station “n” times, wherein “n” denotes a natural number equal to 2 or greater; fifth means for storing “n” output signals of the third means which correspond in timing to the “n” output signals of the second means; sixth means for reading out signals from the fourth means and reading out signals from the fifth means, and for weighing the signals read out from the fourth means in response to the signals read out from the fifth means; and seventh means for combining output signals of the sixth means.
A fourth aspect of this invention provides a direct-conversion receiver comprising a direct-conversion demodulator; first means for detecting a strength of a received signal; a clock signal generator for generating a clock signal in response to a reception start signal, the clock signal having a frequency corresponding to a symbol rate or higher; second means for sampling an output signal of the demodulator at a timing determined by the clock signal; third means for sampling an output signal of the first means at a timing determined by the clock signal; fourth means for weighting an output signal of the second means in response to an output signal of the third means; a memory; an adder for adding an output signal of the memory and an output signal of the fourth means; fifth means for storing an output signal of the adder into the memory, wherein results of the weighting of “n” output signals of the second means which relate to a signal periodically transmitted from a transmitting station “n” times are present in the memory at a final stage, wherein “n” denotes a natural number equal to 2 or greater; and sixth means for reading out signals representative of the results of the weighting from the memory.
A fifth aspect of this invention provides a direct-conversion receiver comprising a direct-conversion demodulator; first means for sampling an output signal of the demodulator; a memory; an adder for adding an output signal of the memory and an output signal of the first means; second means for storing an output signal of the adder into the memory, wherein results of the adding of “n” output signals of the first means which relate to a signal periodically transmitted from a transmitting station “n” times are present in the memory at a final stage, wherein “n” denotes a natural number equal to 2 or greater; and third means for reading out signals representative of the results of the adding from the memory.
A sixth aspect of this invention provides a direct-conversion receiver comprising a direct-conversion demodulator; first means for detecting a strength of a received signal; second means for sampling an output signal of the demodulator; third means for sampling an output signal of the first means; fourth means for weighting an output signal of the second means in response to an output signal of the third means; a memory; an adder for adding an output signal of the memory and an output signal of the fourth means; fifth means for storing an output signal of the adder into the memory, wherein results of the weighting of “n” output signals of the second means which relate to a signal periodically tran
Harada Hiroyuki
Hasegawa Makoto
Kishigami Takaaki
Mimura Masahiro
Tanaka Yasunari
Matsushita Electric - Industrial Co., Ltd.
Tse Young T.
Woo Louis
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