Pulse or digital communications – Receivers
Reexamination Certificate
1999-02-02
2004-06-08
Tse, Young T. (Department: 2634)
Pulse or digital communications
Receivers
C375S247000, C341S143000
Reexamination Certificate
active
06748025
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
This invention relates generally to wireless communication systems. More specifically, the invention relates to signal reception in a wireless communication system.
II. Description of the Related Art
Wireless systems are becoming a fundamental mode of telecommunication in modern society. In order for wireless systems to continue to penetrate into the telecommunications market, the cost of providing the service must continue to decrease and the convenience of using the service should continue to increase. In response to increasing market demand, several industry standard communication techniques have been developed based upon digital modulation schemes. For example, code division multiple access (CDMA), time division multiple access (TDMA) and frequency hopping techniques have been used to develop modern communication systems. As these systems are implemented in parallel with one another, it is often advantageous to have a receiver that is capable of communication using more than one of these standardized techniques. In order to do so, it is necessary to have a receiver that is capable of receiving signals which have been modulated according to several different modulation techniques.
Existing receivers are implemented using double conversion receiver architectures. A double conversion receiver architecture is characterized in that the received RF signal is converted to an intermediate frequency (IF) signal and the IF signal is subsequently converted to baseband. In addition, typically gain control is also applied at the IF. However, double conversion receivers have the disadvantage of utilizing a great number of circuit components, thus, increasing the cost, size and power consumption of the receiver.
A direct conversion receiver provides an alternative to the traditional double down conversion architecture. Direct conversion is characterized in that the received signal is converted directly from the radio frequency at which it is received to baseband. One such technique was disclosed by Williams in U.S. Pat. No. 5,557,642 entitled “DIRECT CONVERSION RECEIVER FOR MULTIPLE PROTOCOLS.”
FIG. 1
is a block diagram showing a direct conversion receiver in accordance with the teachings of Williams. An antenna
20
receives RF signals that have been digitally modulated according to a predetermined standard. The output of the antenna
20
is passed to a low noise amplifier (LNA)
22
. The LNA
22
amplifies the incoming signal. The output of the LNA
22
is coupled to an automatic gain control (AGC) and filtering block
24
. The automatic gain control and filtering block
24
controls the magnitude and spectral content of the received signal. For example, the automatic gain control and filtering block
24
may comprise an anti-aliasing filter in order to prevent out-of-band noise and signals from corrupting the in-band signals of interest during subsequent signal processing. In addition, the automatic gain control and filtering block
24
controls the amplitude of the signal so that it remains within predetermined signal limits of subsequent processing stages. The output of the automatic gain control and filtering block
24
is coupled to an amplifier
26
which further amplifies the signal.
The output from the amplifier
26
is input into a sample and hold circuit
28
. The sample and hold circuit
28
is clocked by a first clock having a frequency f
1
. The output of the sample and hold circuit
28
comprises a series of copies of the modulated signal centered about multiples of the clock frequency f
1
. The output of the sample and hold circuit
28
is coupled to an oversampling delta-sigma converter
30
. The delta-sigma converter
30
receives a second clock having a frequency, f
2
, which is an integer multiple of the frequency f
1
. In this way, the delta-sigma converter loop
30
oversamples the output signal provided by the sample and hold circuit
28
; thus, after decimation filtering providing a quantized representation of the modulated signal.
The construction of the sample and hold circuit
28
requires the use of high frequency circuit elements and design techniques even when the subsampling frequency is relatively low. For example, if a 2 GHz carrier signal is subsampled with a modest 200 MHz clock, a Gaussian sampler model predicts that a root mean-squared (RMS) aperture time—during which the sample and hold circuit samples the signal—of only 6.5 picoseconds would result in introducing a conversion loss of nearly 3 dB. Increasing this aperture time to 16 picoseconds would result in dramatically increasing this conversion loss to 17.6 dB. Timing uncertainties (or jitter) tend to degrade the performance of a subsampler. Using the aforementioned example, an ideal sampler model predicts that a mere 5 picoseconds of RMS jitter limits resolution to 3.7 bits while achieving a resolution of 16 bits requires that RMS jitter be limited to 1 femtosecond.
The sample and hold circuit
28
is typically implemented using some combination of diodes, FET switches or operational amplifiers that typically only operate sufficiently linearly over a small portion of their overall functional voltage range. In addition, the use of subsampling reduces the oversampling ratio that would be achieved by sampling at the carrier frequency or higher thereby significantly reducing the dynamic range of the delta-sigma converter loop
30
. For example, the resolution of a delta-sigma converter is dependent upon the oversampling ratio. First, second, third, and fourth order delta-sigma converters optimally achieve 1.5, 2.5, 3.5, and 4.5 bits of resolution per octave of oversampling ratio, respectively. For example, using 200 MHz sampling clock, the Williams' architecture sacrifices 4.98 bits of resolution (30 decibels (dB)), 8.30 bits of resolution (50 dB), and 11.63 bits of resolution (70 dB), for first, second, and third order delta-sigma converters, respectively, as compared to sampling at the carrier frequency. Recognizing that in a typical system application with a dynamic range requirement of 90 dB or greater, the dynamic range over which the input signal varies is larger than the dynamic range over which subsequent elements, such as the sample and hold circuit
28
and delta-sigma loop
30
, can operate, Williams inserted the AGC and filter circuit
24
before the sample and hold circuit
28
.
The inclusion of the AGC and filter circuit
24
to extend the dynamic range of a receiver is undesirable for spectrally crowded applications such as cellular communications because it makes the receiver sensitivity dependent upon signals and interference that are outside the signal channel. For example, it is possible for a strong signal in an adjacent channel to capture the receiver front end and desensitize the receiver so that a weak signal in the channel of interest is undetectable. In order to avoid this type of operation, the AGC and filter circuit
24
must be capable of rejecting the out-of-band signals before they desensitize the receiver. The resultant filter included in the AGC and filter circuit
24
is typically a tunable narrowband, bandpass filter. Because it is currently not practical to realize such a filter on a semiconductor substrate, inclusion of such a filter significantly increases the cost and complexity of the receiver. Thus, although the AGC portion and LNA portions can be implemented on a high frequency semiconductor substrate, the design requires the signal path to exit the semiconductor for filtering. In order to exit the semiconductor, the signal levels must be increased thereby increasing the size, cost and power consumption of the receiver. In addition, the filter itself is typically implemented using discrete analog components, further increasing the size and cost of the receiver. Finally, the inclusion of automatic gain control creates a DC offset error which is a function of the automatic gain control setting, making offset correction difficult to implement.
Therefore, there has been a need in the industry to deve
Fulwider Patton Lee & Utecht LLP
TechnoConcepts, Inc.
Tse Young T.
Voelzke, Esq. Joel D.
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