Semiconductor device manufacturing: process – Gettering of substrate – By implanting or irradiating
Reexamination Certificate
2005-07-13
2009-02-10
Lindsay, Jr., Walter L (Department: 2812)
Semiconductor device manufacturing: process
Gettering of substrate
By implanting or irradiating
C438S476000, C438S487000, C438S517000, C257SE21127, C257SE21129
Reexamination Certificate
active
07488670
ABSTRACT:
An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming a strained channel region in semiconductor devices. Embodiments include forming a stressor layer over an amorphous portion of the semiconductor device at an intermediate stage of fabrication. The device is masked and strain in a portion of the stressor layer is relaxed. Recrystallizing the amorphous portion of the intermediate device transfers strain from the stressor to the substrate. At least a portion of the strain remains in the substrate through subsequent device fabrication, thereby improving performance of the completed device. In other embodiments, a tensile stressor layer is formed over a first portion of the device, and a compressive stressor layer is formed over a second portion. A tensile stressor layer forms a compressive channel in a PMOS device, and a compressive stressor forms a tensile channel in an NMOS device.
REFERENCES:
patent: 5447884 (1995-09-01), Fahey et al.
patent: 5693546 (1997-12-01), Nam et al.
patent: 5792679 (1998-08-01), Nakato
patent: 5972761 (1999-10-01), Wu
patent: 5989978 (1999-11-01), Peidous
patent: 6046487 (2000-04-01), Benedict et al.
patent: 6069049 (2000-05-01), Geiss et al.
patent: 6271068 (2001-08-01), Hsu et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6657276 (2003-12-01), Karlsson et al.
patent: 6730583 (2004-05-01), Oh et al.
patent: 6808970 (2004-10-01), Feudel et al.
patent: 6890808 (2005-05-01), Chidambarrao et al.
patent: 6900502 (2005-05-01), Ge et al.
patent: 6939814 (2005-09-01), Chan et al.
patent: 6943391 (2005-09-01), Chi et al.
patent: 6952289 (2005-10-01), Fujimoto et al.
patent: 7094671 (2006-08-01), Li
patent: 2002/0055241 (2002-05-01), Oh et al.
patent: 2003/0146494 (2003-08-01), Puchner et al.
patent: 2004/0212035 (2004-10-01), Yeo et al.
patent: 2004/0221792 (2004-11-01), Forbes
patent: 2004/0232513 (2004-11-01), Chi et al.
patent: 2005/0136583 (2005-06-01), Chen et al.
patent: 2005/0224798 (2005-10-01), Buss
patent: 2005/0255667 (2005-11-01), Arghavani et al.
patent: 2005/0260806 (2005-11-01), Chang et al.
patent: 2007/0190741 (2007-08-01), Lindsay
patent: 9-219524 (1997-08-01), None
patent: WO 2006/053258 (2006-05-01), None
Chen, C-H, et al., “Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for Sub-65nm High-Performance Strained-Si Device Application,” 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 56-57, IEEE.
Jae-Geun, O., et al., “Method for Fabricating Semiconductor Device,” Mar. 11, 2003, Hynix Semiconductor Inc., Taiwan English Abstract of TW523869B, 1 Page.
Chi, M.-H., et al., “Modification of Carrier Mobility in a Semiconductor Device,” Jun. 1, 2005, Taiwan Semiconductor Manufacturing Co. Ltd., English Abstract of TW 200518239, 1 Page.
Chen, C.H., et al., “Advanced Strained-Channel Technique to Improve CMOS Performance,” Jul. 1, 2005, Taiwan Semiconductor Manufacturing Co. Ltd., English Abstract of TW 200522348, 1 Page.
Knoefler Roman
Tilke Armin
Infineon - Technologies AG
Lindsay, Jr. Walter L
Pompey Ron E
Slater & Matsil L.L.P.
LandOfFree
Direct channel stress does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Direct channel stress, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Direct channel stress will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4095731