Direct cache coupled network interface for low latency

Details Direct cache coupled network interface for low latency Direct cache coupled network interface for low latency

1993-11-16

1996-11-26

Elmore, Reba I.

395481, 395412, 395427, 3952002, G06F 1312

Patent

active

055795030

ABSTRACT:
A low latency network receive interface reduces the copying of message data by directly coupling the network to a cache and by providing an address-based message in which an incoming message block preincorporates an address so that messages can be directly stored in their final destination. In a preferred embodiment, the message data size is made equal to the cache block size so that cache blocks can be updated atomically. The small message size--which is equivalent in size to a cache block--also reduces transfer time, unlike Direct Memory Access (DMA) approaches in which a large amount of data must accumulate prior to transfer to main memory as a block. In one embodiment, the cache to which message data is directly coupled is divided into a message cache and a data cache, with the incoming message block coupled directly to the message cache. When an incoming message arrives, its address is compared with addresses in the data cache, with the data in the data cache at this address being purged in an invalidation process if the particular address is priorly occupied. The processor first accesses the data cache, and if no valid data exists at the corresponding address, it accesses the memory cache, which is in turn followed by accessing main memory if no valid cache data exists. This direct cache coupling of incoming message data eliminates latency due to buffering of the incoming message data in temporary storage prior to copying the message data.

REFERENCES:
patent: 4392200 (1983-07-01), Arulpragasam
patent: 4823259 (1989-04-01), Aichelmann, Jr. et al.
patent: 5274782 (1993-12-01), Chalasani et al.
patent: 5440698 (1995-08-01), Sindhu et al.

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