Direct attach of interrupt controller to processor module

Details Direct attach of interrupt controller to processor module Direct attach of interrupt controller to processor module

2001-11-21

2002-12-17

Nelms, David (Department: 2818)

Multiplex communications

Channel assignment techniques

Details of circuit or interface for connecting user to the...

C370S419000, C370S420000, C370S484000, C370S487000, C712S031000, C712S028000, C712S033000, C712S034000

Reexamination Certificate

active

06496517

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to methods and devices for solving the problem of latency in servicing interrupts in a system, such as in an AMBA based system. The present invention more specifically relates to a method and device wherein an interrupt controller is coupled directly to a processor so that the processor can access the interrupt controller without having to access a system bus.
Advanced Microcontroller Bus Architecture (AMBA) is a very popular bus architecture developed by ARM Ltd., and is used by application specific integrated circuit (ASIC) vendors world-wide. AMBA is a family of buses which includes Advanced System Bus (ASB), Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB), where AHB is typically used as a multi-master/multi-slave system bus and APB as a simplified single master peripheral bus. AMBA is used in many applications, such as wireless, telecommunications, networking, office automation, and storage. Interrupt controllers typically reside on an AMBA bus, however, a problem with AMBA based systems is latency in servicing interrupts. The problem is typically alleviated either by one or both of the following:
employing a vectored interrupt controller to accelerate the prioritization of interrupts and calculating the interrupt service routine starting address; and/or
by moving the interrupt controller close to the processor to reduce the access time.
A vectored interrupt controller reduces latency by determining in hardware the interrupt that needs servicing by resolving predefined priorities and then passing to the central processing unit (CPU) an index, instruction address or other tag that the CPU can use to handle the interrupt. Typically, this can be performed much quicker in hardware than within a software based scheme as is used in a non-vectored interrupt controller. The software based scheme adds latency in determining which interrupt to service.
With regard to having the interrupt controller be close to the processor,
FIGS. 1 and 2
illustrate two typical AMBA systems. Each system includes a processor
10
, an EPROM/SRAM controller
12
and internal SRAM
14
, all on a higher bandwidth pipelined main system bus (AHB bus)
16
. In both FIGURES, the processor
10
is shown as being an “ARM processor”, i.e. a processor from ARM Ltd. ARM Ltd. manufactures general purpose Reduced Instruction Set Computing (RISC) processors which are popular in the industry for the applications listed above. Each system also includes a Universal Asynchronous Receiver/Transmitter (UART)
18
, timers
20
, and General Purpose Input/Output (GPIO)
22
, all on a secondary bus (APB bus)
24
. An AHB/APB bridge
26
effectively connects the AHB bus
16
to the APB bus
24
. While in
FIG. 1
the interrupt controller
30
is on the APB bus
24
as a slave peripheral for the processor
10
to access, in
FIG. 2
the interrupt controller
30
is on the AHB bus
16
.
Both of the arrangements shown in
FIGS. 1 and 2
present several disadvantages with regard to the processor
10
attempting to gain access to the interrupt controller
30
. In both of the arrangements, the interrupt controller
30
is physically far away form the processor
10
, and the processor
10
has to arbitrate and win the AHB bus
16
in order to access the interrupt controller
30
. Depending on the number of masters on the AHB bus
16
, it could take numerous clock cycles for the processor
10
to win the AHB bus
16
. Additionally, in some systems, the processor is running at a higher speed than the AHB bus. This increases the number of processor clock cycles required to access the interrupt controller. With regard to the arrangement shown in
FIG. 1
, the processor
10
has to also cross the AHB/APB bridge
26
in order to access the interrupt controller
30
. This presents an additional delay. Still further, in some systems, the AHB bus is at a higher speed than the APB bus. If the interrupt controller is located on the APB bus (as shown in FIG.
1
), this increases the number of processor clock cycles required to access the interrupt controller.
OBJECTS AND SUMMARY
A general object of an embodiment of the present invention is to provide a system wherein a processor can access an interrupt controller without having to access a system bus.
Another object of an embodiment of the present invention is to provide a system wherein a processor does not have to access a bus to communicate with a vectored interrupt controller, thereby leaving the bus free for other masters and providing overall improved system performance.
Still another object of an embodiment of the present invention is to provide a system wherein a processor can quickly access an interrupt controller at the processor clock speed without having to access a system bus.
Still yet another object of an embodiment of the present invention is to provide a system wherein a processor can quickly access not only data SRAM, but also an interrupt controller, at the processor clock speed without having to access a system bus.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a system, such as an AMBA based system, wherein an interrupt controller is coupled directly to a processor, thereby providing that the processor can access the interrupt controller without having to access a system bus. Specifically, the interrupt controller may be coupled to a port of the processor, such as a tightly coupled memory (TCM) port or a coprocessor port of the processor. The interrupt controller may be coupled to the TCM port along with SRAM.


REFERENCES:
patent: 6353619 (2000-03-01), Banas et al.
patent: 6330658 (2001-12-01), Evoy et al.

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