Direct alignment of contacts

Details Direct alignment of contacts Direct alignment of contacts

2002-05-08

2004-11-09

Vigushin, John B. (Department: 2841)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C174S255000, C174S262000

Reexamination Certificate

active

06815812

ABSTRACT:

FIELD
This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to integrated circuit packaging.
BACKGROUND
Traditionally, all of the various components of an integrated circuit were powered at a single voltage level. However, in more recent technologies, different components of an integrated circuit are powered from different voltage sources. For example, in some new technologies the core of an integrated circuit, such as the memory or logic components, is powered off of one voltage source, and the input output components of the integrated circuit are powered off of a different voltage source. Typically, the core voltage level, generally designated as VDDcore, is nominally 1.2 volts or less and the input output voltage level, generally designated as VDDio, is nominally 3.3 volts. Each of these two voltage supplies to the integrated circuit also has associated with it a so called ground circuit, which for the core voltage is designated as VSScore and for the input output voltage is designated as VSSio. In addition to these connections to the integrated circuit, connections for the signals to and from the integrated circuit must also be made.
In a flip chip package design, small balls of solder, called bumps, are placed between electrical contacts on the surface of the integrated circuit and electrical contacts on the top most surface of a package substrate. The solder bumps provide the electrical interface between the integrated circuit and the package, which also provides the electrical interface to other components. The top most surface of the package substrate is typically referred to as the redistribution layer. One reason for this is that there are typically so many connections between the integrated circuit and the package substrate, that all of the electrical connections cannot be routed out on a single layer. Thus, the redistribution layer receives electrical connections from the integrated circuit, and redistributes the signals to a plurality of different levels to be routed out.
As the complexity of integrated circuits has increased, or in other words, as the number of devices within an integrated circuit has increased, the number of desired electrical connections to the integrated circuit has also increased. At the same time, the physical size of integrated circuits has decreased. Thus, an ever expanding number of electrical connections must be made within an ever decreasing surface area. This has created problems with finding the physical space in which to form the electrical connections. Adding to this problem is the increase in power and ground connections that is required by having two different voltage levels for the core and the input output components as mentioned above.
Typically, the redistribution layer has bus lines in one or more orthogonal direction, to which the VDDcore and VSScore contacts are electrically connected, and which extend substantially completely across the redistribution layer, at least in those areas which the VDDcore and VSScore contacts are disposed. These bus lines are then dropped down one or two layers through electrical vias to a VDD mesh layer and a VSS mesh layer. One benefit of this design is that the layout of the mesh layers do not need to match the layout of the VDD contacts and VSS contacts on the integrated circuit, because the bus lines on the redistribution layer can be arranged so as to make appropriate connections between the two designs.
However, this design also has problems, in that the signal and other traces must be routed around the bus lines. This tends to severely restrict where the signal traces can go on the redistribution layer, typically resulting in signal traces that are longer, thinner, and more closely spaced together than would otherwise be necessary. All of these conditions tend to increase the resistance capacitance delay of signals carried on the traces.
What is needed, therefore, is an integrated circuit and package design in which VDDcore, VSScore and other electrical connections between the integrated circuit and the package are more efficiently arranged.
SUMMARY
The above and other needs are met by a packaged circuit according to a preferred embodiment of the present invention. An integrated circuit is fabricated with VDDcore contacts in first known positions and VSScore contacts in second known positions. A VDDcore mesh layer is fabricated with traces, and a VSScore mesh layer is fabricated with traces. A redistribution layer is disposed adjacent the integrated circuit, and overlies the VDDcore mesh layer and the VSScore mesh layer.
First contacts in the redistribution layer are positioned in alignment with the first known positions, to make electrical connections between the redistribution layer and the VDDcore contacts. Second contacts are positioned in alignment with the second known positions, to make electrical connections between the redistribution layer and the VSScore contacts.
First electrically conductive vias are positioned in alignment with the first known positions, to make electrical connections between the first contacts and the VDD mesh layer, without using a VDDcore bus that extends substantially across the redistribution layer. The traces of the VDD mesh layer are positioned in alignment with the first known positions. Second electrically conductive vias are positioned in alignment with the second known positions to make electrical connections between the second contacts and the VSS mesh layer, without using a VSScore bus that extends substantially across the redistribution layer. The traces of the VSS mesh layer are positioned in alignment with the second known positions.
By aligning all of the VDDcore contacts on the integrated circuit, the first contacts and the first vias on the redistribution layer, and the traces on the VDD mesh layer, a VDDcore bus that extends substantially across the redistribution layer is not required, and the redistribution layer is freed up for use by the signal and other traces. For example, the signal traces can be more directly routed, wider, and more broadly spaced because a VDDcore bus does not take a substantial portion of the surface area of the redistribution layer. Further, By aligning all of the VSScore contacts on the integrated circuit, the second contacts and the second vias on the redistribution layer, and the traces on the VSS mesh layer, a VSScore bus that extends substantially across the redistribution layer is not required, which frees up addition surface area of the redistribution layer. Thus, a packaged circuit according to a preferred embodiment of the present invention overcomes the problems as mentioned above.
In various preferred embodiments of the invention, the VDD mesh layer and the VSS mesh layer immediately underlie the redistribution layer, while in alternate embodiments intervening layers are disposed between the VDD mesh layer and the VSS mesh layer and the redistribution layer. In one embodiment, at least one of a VDDcore bus and a VSScore bus is disposed on the redistribution layer. However, in this embodiment the bus or buses are limited to no more than about one quarter of the redistribution layer. Such limited size buses can be used in a portion of the integrated circuit that has high VSScore or VDDcore requirements. However, the limited use of the surface area of the redistribution layer for such purposes still allows for the benefits as mentioned above.
According to another aspect of the invention there is provided an integrated circuit package. A VDDcore mesh layer is fabricated with traces, and a VSScore mesh layer is fabricated with traces. A redistribution layer overlies the VDDcore mesh layer and the VSScore mesh layer. The redistribution layer is designed to receive an integrated circuit having VDDcore contacts in first known positions and VSScore contacts in second known positions. First contacts in the redistribution layer are positioned in alignment with the first known positions, to make electrical connections between the redistribution layer an

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