Diode formed in integrated-circuit structure

Details Diode formed in integrated-circuit structure Diode formed in integrated-circuit structure

1977-06-20

1978-09-26

Edlow, Martin H.

357 35, 357 40, 357 86, H01L 2704

Patent

active

041175077

ABSTRACT:
An IC chip with a substrate 10 of one conductivity type (P), overlain by an epitaxially grown layer 12 of the opposite conductivity type (N), includes a diode formed in part by a region 16 of that layer separated from other such isolated regions by a barrier 14 of the first conductive type (P), the remainder of the diode being constituted by an insular central zone 18 of the first conductivity type (18) within that region. To minimize leakage losses when the diode is forwardly biased, a low-resistance zone 22, 32 of the second conductivity type (N+) is interposed between the central zone 18 and the barrier 14, joining a buried low-resistance stratum 30 of the same conductivity type (N+) which lies between region 16 and substrate 10. A first diode electrode (anode) 34 is formed by a metallic coating 34 which covers an upper surface of central zone 18 but is in contact, over most of its area, with an annular low-resistance section 36 of the second conductivity type (N+) embedded in that zone to reduce the number of charge carriers (holes) injected into the diode during forward conduction. A second diode electrode (cathode) consists of a metallic coating 24, 24' in contact with the low-resistance zone 22, 32 surrounding the central zone 18. Between these two zones lies an annular collector zone 40, 40' of the first conductivity type (P) in contact with the second electrode 24', or with an extension 24" thereof, which may extend the buried stratum 30 and which further reduces the flow of charge carriers (holes) toward the substrate during forward conduction.

REFERENCES:
patent: 3590345 (1971-06-01), Brewer
patent: 3969748 (1976-07-01), Horil
patent: 4027325 (1977-07-01), Genesi
patent: 4047220 (1977-09-01), Ferro

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