Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1998-08-19
2002-02-05
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S622000, C438S623000, C438S668000, C257S700000, C257S758000, C257S774000
Reexamination Certificate
active
06344371
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to a dimensionally stable core for high density chip packages which reduces material movement variability during the processing and the manufacture of the chip packages. The stable core, which provides the stability to the high density chip package, is preferably formed from a metal and includes concurrently formed dielectric and metal layers. Vias are subsequently formed to permit the manufacture of a high density chip package.
BACKGROUND OF THE INVENTION
High density chip package substrates require many vias which connect the input/output (I/O) of an integrated circuit chip to routing layers or power/ground layers buried within the chip package substrate. Conventional mechanical drilling processes which have been used in the past for the formation of vias are being replaced with laser via drilling processes. Laser via drilling processes offer the potential to form vias much more rapidly, and at less cost, than conventional mechanical drilling processes. To enable this rapid rate of via production, it is advantageous to use dielectrics which are thinner than those which have been used in the past. The thin dielectrics allow the formation of micro vias, i.e., vias <100 microns in diameter.
To effectively metallize these micro vias after they have been formed, the aspect ratio (the via's height divided by its diameter) must be maintained at a predetermined value. For example, for blind vias, the aspect ratio must be approximately one to insure that conventional metallization methods will be adequate to deposit a sufficient amount of metal onto the wall surface of the micro blind via.
As should be understood, it is disadvantageous to form micro blind vias in a dielectric material that contains a woven glass reinforcement. More particularly, if a woven glass reinforced dielectric is used, the laser power required to ablate the woven glass is as high as the laser power required to ablate a buried copper pad on the layer to which the blind via is to provide connection. Accordingly, the laser will penetrate the copper pad and continue into layers below, thus extending the via. After metallization, the unintentionally extended via will short to subsequent layers, causing the entire circuit to be scrapped.
In order to solve the shortcomings associated with forming micro blind vias in a dielectric material containing woven glass, dielectric material manufacturers have introduced thin, unreinforced prepregs to replace conventional glass reinforced prepregs. However, the use of such thin, unreinforced prepregs has caused other difficulties in the production of high density printed circuit boards and chip package substrates. More particularly, the elimination of woven glass from the dielectric material has reduced the dimensional stability of a chip package substrate. When thermosetting resins are used as a component of the dielectric material, these resins commonly induce shrinkage in a multilayer circuit board, or chip package substrate, upon lamination and curing of the resins. The shrinkage is limited to the order of a few thousand parts per million at most, and is not in itself a manufacturing problem, as the shrinkage can be compensated for when the artwork for the substrate is produced. However, variability in the degree of shrinkage exists, even for one unchanging circuit design. This variability in the degree of shrinkage can lead to reduced yields in high density printed circuit boards and chip packaging substrates. For example, if one of the internal layers in a multilayer circuit board is a ground or power layer consisting of a plane of copper, and if vias have to pass through clearances in this layer, the shrinkage variability induced during lamination can result in a variable location of the ground clearances from panel to panel. When vias are drilled in these circuits, some percentage of these vias may miss the clearances in the ground or power layer and strike the copper. After metallization, these vias would be shorted to the ground or power layer, resulting in a scrapped circuit.
There exists a need for a dimensionally stable core to facilitate the manufacture of high density chip packages having dielectric materials unsupported by woven glass.
SUMMARY OF THE INVENTION
The present invention includes a method of manufacturing high density chip package substrates by processing circuit layers concurrently on both sides of a metal core, which is preferably made of copper. The copper core improves the dimensional stability of thin, unreinforced dielectric materials used in the substrate. As a result of the metal core, material movement is reduced during lamination, which facilitates the processing and manufacture of the high density chip package. The metal core also provides buried capacitance which helps reduce simultaneous switching noise on the chip.
The dimensionally stable core of the present invention includes a metal core having at least one clearance etched therethrough, a dielectric layer on both sides of the metal core and filling the clearance, a metal cap layer on both sides of the dielectric layer, and drilled vias in the metal core through the metal cap layer. When the metal core is to be electrically isolated, vias are formed to extend through the metal cap layer, the dielectric layer and the clearance in the metal core, thus isolating the metal core. A metal layer is deposited on the wall surfaces of such vias. The dielectric layer and metal cap layer can be placed concurrently on top and bottom surfaces of the metal core. Additional dielectric layers and metal cap layers can again be concurrently laminated on top and bottom surfaces of the cap layers in a similar fashion. Additional vias, where necessary, are formed. Repeatedly adding dielectric and metal caps layers, and vias provides a dimensionally stable, high density chip package.
The metal core and the metal layers can be copper, or any other suitable metal, such that the coefficient of thermal expansion (CTE) of the chip package matches the CTE of the printed circuit board. The dielectric can be any unsupported prepreg. Further, the vias can be blind vias or through vias. The vias are drilled using a laser which ablates material as it drills.
A method for fabricating a dimensionally stable core according to the present invention includes providing a metal core, such as copper, placing dielectric layers on top and bottom surfaces of the metal core, placing metal cap layers, such as copper, on top and bottom surfaces of the dielectric layer and laminating the dielectric and metal cap layers together and to the metal core. The method further includes drilling vias through the metal cap layers, dielectric layers and the metal core, or clearances in the metal core, and then repeating the steps to form a multi-layer high density chip package.
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Fischer Paul J.
Gorrell Robin E.
Sylvester Mark F.
Díaz José R
Genco Vic
Lee Eddie
Sheets Eric
W. L. Gore & Associates, Inc.
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