Coded data generation or conversion – Analog to or from digital conversion – Nonlinear
Reexamination Certificate
2001-10-17
2002-12-17
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Nonlinear
C341S159000
Reexamination Certificate
active
06496126
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a digitization apparatus and a digitization method for the transfer of data, more particularly, to a digitization apparatus and a digitization method, which has more flexibility, higher accuracy and faster speed to digitize data received from mass storage devices.
2. Description of Related Art
Optical mass storage devices such as compact disk read only memory (CD-ROM) devices are used for the storage and distribution of programs and data structures. Recently, as the technology being developed the mass storage device such as a CD-ROM device has been improved and more and more powerful functions are introduced thereon.
FIG. 1
shows a conventional architecture of a CD-ROM device. A spindle motor
8
drives a disk
1
rotation and an optical pickup element
2
reads the data from the disk
1
and transmits the data to an amplifier
3
. The amplifier
3
amplifies the received data and outputs a RF signal to a digitization apparatus (slicer)
4
. The digitization apparatus
4
converts the RF signal into the binary EFM (Eight to Fourteen Modulation) signal, which is then sent to a phase locked loop (PLL) circuit
5
and a data processing circuit
6
.
The PLL circuit
5
generates a clock signal PLCK according to the EFM signal and outputs the clock signal PLCK to the digitization apparatus
4
and the data processing circuit
6
. The date processing circuit
6
generates a system reference clock signal XCK, which is sent to the motor control circuit
7
. The date processing circuit
6
also generates output signal according to the EFM signal and the clock signal PLCK. The motor control circuit
7
is used to control the motor
8
rotating at a desired speed with respect to the system reference clock signal XCK. A system controller
9
is used to output a motor speed control signal HS to the data processing circuit
6
and the motor controller
7
to adjust the data processing speed and the rotating speed of disk
1
.
Conventionally, to reduce the bias current or voltage of digital data while transmitting, methods to decrease the sum of coded digital data to almost zero are introduced. In a conventional design method, the digitization apparatus is used to digitalize the transmitted data, which is coded by the method of decreasing the sum of coded digital data to almost zero.
FIG. 2
shows a conventional digitization apparatus, which is introduced in U.S. Pat. No. 6,157,603. The digitization apparatus
20
includes a comparator
21
, an up/down counter
22
, a multiplexer
23
, two frequency dividers
24
and
25
, and a digital/analog converter
26
. The comparator
21
compares the RF signal supplied from the amplifier
3
shown in
FIG. 1
, with a reference voltage Vref generated by the digital/analog converter
26
, and generates the EFM signal. An operating clock signal CK is provided by either the frequency divider
24
or the frequency divider
25
through selection of the multiplexer
23
. The multiplexer
23
is controlled by a LOCK signal. The frequency divider
24
receives the clock signal PLCK generated by the phase locked loop (PLL) circuit, while the frequency divider
25
receives the clock signal XCK generated by an oscillator, for example, a voltage controlled oscillator or crystal oscillator.
Based on the operating clock signal CK from the multiplexer
23
, the up/down counter
22
serves as a differential data calculator which integrates a differential value between the periods of EFM signal “0” and “1” supplied from the comparator
11
, and outputs a differential data. The digital/analog converter
26
converts the differential data from the up/down counter
22
into the reference voltage Vref, and supplies to the ads to comparator
21
.
The RF signal and the reference voltage Verf are sent to the non-inverted and inverted inputs of the comparator
21
, respectively. The comparator
21
compares the RF signal with the reference voltage Vref, and converts the RF signal into the EFM signal. The EFM signal of the comparator
21
is sent to the up/down control input of the up/down counter
22
. Because the up/down counter
22
is clocked by the operating clock signal CK, and counts down when the EFM signal is “0” and counts up when the EFM signal is “1”, the integration of the difference between the 1 and 0 of the EFM signal is generated by the up/down counter
22
. The D/A converter
26
receives the integration of the difference and converts the integration into the analog voltage Vref. Thus, the comparator
21
can slice the RF signal based on the analog voltage Vref to generate the EFM signal, which has almost equal binary code periods.
As shown in
FIG. 2
, the operating clock signal CK is generated by the frequency divider
24
, which divides the clock signal PLCK, or by the frequency divider
25
, which divides the clock signal XCK. If the up/down counter
22
uses the operating clock signal CK as the input clock to count the EFM signal, the accuracy of the slice circuit will be greatly reduced, due to that the operating clock signal CK is divided. However, if the up/down counter
22
uses the clock signal PLCK or XCK as the input clock to count the EFM signal, the operational speed will be limited by the counting speed of the up/down counter
22
.
SUMMARY OF THE INVENTION
To solve the above problems, the objective of the invention is to provide a digitization apparatus and method to digitalize signal with more flexibility, better accuracy and higher-speed.
To attain the objective previously mentioned, this invention digitization apparatus includes a digitizer, a finite state machine, and a digitizer parameter adjustment element. The digitizer receives an analog signal and converts it into a parallel digital signal. The finite state machine generates a state signal in response to the parallel digital signal. The digitizer parameter adjustment element generates a adjusting signal according to the state signal generated from the finite state machine. The digital signal of the digitizer varies in accordance with the adjusting signal.
In the digitization apparatus above-mentioned, the digitizer further includes a comparator and a serial-to-parallel converter. The comparator compares the analog signal and the adjusting signal and generates a serial sequence of logic signals. The serial-to-parallel converter converts the serial sequence of logic signals into the parallel digital signal.
In the digitization apparatus above-mentioned, the finite state machine further receives a gain control signal. The state signal of the state machine is determined by the parallel digital signal and the gain control signal.
REFERENCES:
patent: 5638072 (1997-06-01), Van Auken et al.
patent: 6157603 (2000-12-01), Okubo et al.
patent: 6388500 (2002-05-01), Lee et al.
Chang Andrew C.
Ho Chi-Kwong
Zhan Jing-Hong Conan
J. C. Patents
Mediatek Inc.
Wamsley Patrick
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