Digitally synthesized multiple phase pulse width modulation

Details Digitally synthesized multiple phase pulse width modulation Digitally synthesized multiple phase pulse width modulation

1999-10-19

2001-04-24

Patel, Rajnikant D (Department: 2838)

Electric power conversion systems

Current conversion

Having plural converters for single conversion

C363S071000, C323S285000

Reexamination Certificate

active

06222745

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a power converter and in particular to a DC to DC power converter which uses variation in pulse width, also referred to as variable duty cycle, to an control output voltage.
2. Description of the Related Art
DC to DC power conversion is used to provide a regulated DC output voltage of a lower value to a load from an unregulated higher input voltage as a source. In most applications, the input is a voltage source and the output of the DC to DC converter is precisely controlled to maintain a predetermined voltage regardless of variations in the load current; in other words, the load current is an independent variable. An example of an application of DC to DC power conversion is in a personal computer, wherein the power supply for the computer has a 12 volt DC output for powering all internal components of the computer. The power demands vary depending on the components drawing power at the time. The processor for the computer requires a lower operating voltage, for example, 3.3 volts DC, which must be derived from the 12 volt supply. The proper operation of the processor demands that the voltage supplied to the processor be tightly controlled, regardless of variations in the 12 volt signal. An example of such an application is shown in
FIG. 1
, wherein a computer
20
has a power supply PS, also referenced
22
, that is either a battery or an AC to DC converter from line power. A DC to DC power converter
24
receives the output of the power supply PS, reduces it to a controlled DC level of, for example, 3.3 volts and supplies it to a microprocessor chip
26
. New technology is being introduced which requires voltages lower than 3.3 volts, such as a 1.2 volt supply instead of a 3.3 volt supply to the microprocessor
26
. This is generated from the 12 volt power supply
22
, which represents a ten fold drop in the voltage from the source to the load of the power converter
24
and presents an even greater difficulty of accurate control of the voltage to the load that the 3.3 volt load.
The power converter
24
may be visualized as composed of two functional parts, namely a power conversion stage
28
and a controller stage
30
, as shown in FIG.
2
. The power conversion stage
28
receives the input or source voltage V
in
to the power converter
24
, such as from the power supply
22
of FIG.
1
and supplies the regulated output voltage V
out
to the load, such as to the microprocessor
26
. The controller
30
monitors the output of the power conversion stage
28
by a connection
33
and compares it to a reference voltage V
ref
received at a reference input
32
and sends a control signal over a control lead
34
to the power conversion stage
28
to adjust the voltage of the output, if necessary.
A variety of methods of control have been utilized for power conversion in controlled voltage applications. One such approach is pulse width modulation. Pulse width modulation is utilized in DC to DC power converters for efficiently transferring power from the input source to an output load, i.e. without draining off the excess as heat using a dissipative element, for example. A conventional approach to pulse width modulation is to use an integrating amplifier, for example, as the controller
30
, to generate an error signal based on a difference between the desired output voltage V
out
and a predetermined reference voltage V
ref
. An analog-to-digital (A-to-D) conversion is performed by comparing the analog error signal from the integrating amplifier to an analog sawtooth signal or triangular-shaped waveform signal using an analog comparator to convert the analog error signal to a digital clock signal. The A-to-D conversion produces a variable duty cycle clock signal that is proportional to the analog error signal. The variable duty cycle clock signal is used within a DC-to-DC converter circuit, such as the power conversion stage
28
, to selectively control the transfer of power from the input source to the output load to achieve the desired output voltage. In other words, the power conversion stage
28
turns on for the duration of the pulse and off at the end of the pulse. The output is averaged to achieve the output voltage V
out
. The variable duty cycle control signal changes the proportion of the time that the power converter stage
28
is on. Thus, pulse width modulation architectures require the use of an analog sawtooth or a triangular-shaped waveform for converting the analog error signal to a variable duty cycle digital clock signal.
The need for innovation beyond the afore-described power conversion architecture is recognized when more power is required than can be handled by a single power conversion stage. In particular, the power transfer from the input source
22
to the output load
26
exceeds the allowable capacity or the practical size of a single power conversion stage
28
. Delivery of more power is accomplished by providing multiple power conversion stages
36
, as illustrated in
FIG. 3
, each supplying a portion of the total output power. Each stage
36
is of like kind and quality. In a DC-to-DC converter, the power conversion stages are comprised of transistors, inductors and/or transformers, capacitors, and diodes which are assembled for transferring power at a predetermined frequency. Each of the stages
36
in a multiple stage power supply has the same components which are matched to the limits of their parasitic characteristics and connected in the same circuit configuration.
In
FIG. 3
, each power conversion stage
36
is controlled by the variable duty cycle clock signal
34
to control the transfer of power from its input to its output. While each stage
36
would carry a portion of the load, any mismatch in characteristics results in an imbalance of the power from the respective stages. Further, by controlling all stages
36
from a single clock signal
34
, all of the stages
36
turn on and turn off simultaneously. This creates undesirable large transient load conditions for the source.
Another requirement for multiple stages occurs when a need for increasing the effective power transfer frequency of the DC-to-DC converter is seen. Each of the stages operates at a predetermined frequency. Providing multiple stages operating shifted in time increases the power transfer frequency without costly high frequency power conversion stages. Operating the stages shifted in time also avoids the simultaneous turn on and turn off of the stages, thereby placing less strain on the source. Such multiple stages
36
require multiple, variable duty cycle clock signals, matched in duty cycle and frequency yet shifted in time and generated from a single analog error signal, to drive them. In particular, since all of the power conversion stages
36
are connected in parallel and are of like kind and quality, it is required that each clock signal operate at the same frequency and the same duty cycle to provide a balance in the power handled by the individual stages
36
.
FIG. 4
illustrates a power converter construction which is capable of such multiphase time shifted operation. Instead of the single control signal
34
to the stages
36
as in
FIG. 3
, the converter
40
of
FIG. 4
produces separate control signals
38
for each of the stages
36
. Phase shifting the control signals
38
to the stages
36
, in other words, spacing the variable duty cycle clock signals from one another in time such that no two clock signals are coincident in time avoids the simultaneous turn on and turn off of the stages
36
and achieves an effectively higher power transfer frequency. For example, two power conversion stages
36
controlled by two coincident, 500 kHz variable duty cycle digital clock signals
34
(as in
FIG. 3
) results in the transfer of power at a 500 kHz rate. However, two power conversion stages
36
, each controlled by a variable duty cycle 500 kHz digital clock signal
38
spaced at a 180° phase relation to each other results in the transfer of power at

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