Digitally self-calibrating circuit and method for pipeline ADC

Details Digitally self-calibrating circuit and method for pipeline ADC Digitally self-calibrating circuit and method for pipeline ADC

2000-06-08

2002-04-09

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S120000

Reexamination Certificate

active

06369744

ABSTRACT:

BACKGROUND OF THE INVENTION
The performance of a switched capacitor pipeline ADC is very sensitive to (1) mismatch in the capacitors thereof, (2) variation in the finite gain of the operational amplifiers therein, (3) to the accuracy of the reference voltage applied to each stage and (4) charge injection from the switches of the switched capacitor circuitry. Several self-calibration techniques/structures have been described in the prior art.
FIG. 1A
shows a 1-bit per stage pipeline ADC of a self-calibrating pipeline ADC described in prior art U.S. Pat. No. 5,499,027 (Karanicolas et al.), with a sample-hold stage
12
followed by N multiply-by-two stages of
14
-
1
,
14
-
2
etc. Each multiply-by-two stage has an analog input, a one-bit digital input, an analog output, and a one-bit digital output. For example, multiply-by-two stage
14
-
1
receives analog input
20
and digital input
22
, and produces analog output
24
and digital output
26
. Multiply-by-two stage
14
-
2
receives analog input
24
and digital input
26
, and produces analog output
24
-
2
and digital output
26
-
2
. The sample and hold stage and the multiply-by-two stage each utilize a single comparator to generate the respective digital output bits. The digital self calibration circuitry is not shown in
FIG. 1A
, but is shown in
FIGS. 1B and 1C
. The quantized representation of Vin is D
0
, D
1
, D
2
. . . , which is the data word X in
FIGS. 1B and 1C
.
U.S. Pat. No. 5,499,027 (the '027 patent) explains that if the residue exceeds the reference boundary due to charge injection offset, comparator offset, or capacitor mismatch, this results in missing decision levels which result in missing codes and consequently in errors in the output word X. The '027 patent explains that missing codes are caused whenever the output of any stage in a radix 2 pipeline ADC exceeds the reference boundary, and that the gain G should be substantially less than 2 in the stages to be calibrated, in order to prevent the residue from being outside of the reference boundary and causing the missing decision levels and the resulting missing codes.
It should be understood that the Vin vs. Dout transfer characteristic of an ideal pipeline ADC is a straight line. The above mentioned missing codes produce discontinuities in the ideal transfer characteristic so that it is not a straight line. The purpose of the self-calibrating described in the '027 patent is to “smooth out” the discontinuities introduced into the transfer characteristic by the missing codes.
FIGS. 1B and 1C
illustrate the recursive self calibration digital logic for calibrating multiply-by-two stage
11
first, and later calibrating MX
2
stage
10
, etc. The '027 patent describes pipeline ADC
10
as having the first 11 stages with gains set to 1.93 and the last six stages with gains set to 2. The calibration operation begins by calibrating the 11
th
stage, and then continues by calibrating the 10
th
stage, and continuing stage by stage to the first stage
14
-
1
. The gain of 1.93 was chosen to ensure enough gain reduction that the residue never exceeds the reference boundary even in the worst case when the maximum capacitor mismatch, maximum comparator offset, and maximum charge injection error magnitudes are summed together.
In
FIG. 1B
, the outputs D of “stage
10
” (not shown) and X of stages
11
-
17
are provided to digital calibration logic
40
along with stored calibration constants S
1
and S
2
previously determined and stored for stage
11
. S
1
and S
2
correspond to the values of the data word X when Vin is equal to 0 and D equals 0 and D equals 1, respectively. The digital self calibration process for each stage is described by Y=X if D=0, and Y=X+S
2
− S
2
if D=1, where D is that the decision, X is the “raw code” digital output word and Y is the “transformed code” digital output word. S
1
-S
2
is stored for each of the calibrated stages
0
-
11
. To initially determine S
1
for stage
11
, the analog input is set to 0 and the input bit for stage
11
is forced to 0. The quantity X in this condition is S
1
for stage
11
, and then the input bit for stage
11
is forced to 1 and in that condition the quantity X is S
2
for stage
11
.
With the digital calibration of stage
11
accomplished, the digital calibration of the next most significant stage
10
can proceed in the same Fashion, as illustrated by FIG.
1
C. Similarly, with the digital calibration of stage
10
accomplished, the digital calibration of the next higher stage
9
can proceed in the same fashion, and so forth all the way to stage
1
. Since the digital self calibration aligns the points S
1
and S
2
using values measured under the same conditions as during the normal conversion, the digital self calibration automatically accounts for capacitor mismatch, charge injection, and finite operational amplifier gain.
It is important to recognize that the switches in blocks
14
-
1
and
14
-
2
, which function as digital-to-analog converters, operate so as to connect the lower input of each analog summer to either −V
ref
or +V
ref
. If the gain of the amplifier
18
-
1
and amplifier
18
-
2
is exactly 2 or slightly greater, the self-calibrating ADC “clips” the digital output thereof because the calibrating occurs at a level close to the full scale output value. Stated differently, if the gains of the stages to be digitally calibrated are too close to 2, then the ADC “over-ranges” its output. The digitally self calibrated pipeline ADC of the '027 patent therefore uses a reduced gain of 1.93 for the amplifiers
18
-
1
and
18
-
2
and the corresponding amplifiers in all of the self-calibrating stages in order to ensure that the maximum raw digital output value is less than full scale under the worst case condition of maximum capacitor mismatch, maximum comparator offset, and maximum charge injection error magnitude. This enables the self-calibrating ADC of the '027 patent current to accomplish digital self calibration using subtraction only, which is much less complex than using an adder-subtracter.
Most practical implementations of the pipeline ADC disclosed in the '027 patent would be fully differential. A major problem with the self-calibrating pipeline ADC of the '027 patent is that if the differential input signal is very small in magnitude (as often is the case), the worst case transitions from all “1”s to all “0”s would occur at the zero-crossing points, i.e., at ground or zero volts. The distortions in the digital output signal would be caused by the input offset voltages of the comparators. Such distortions usually would be disproportionately large compared to the amplitudes of the low amplitude differential input signals, and of course, the associated low SNR (signal to noise ratio) would be very undesirable.
The described reduction of the gain G in the '027 pipeline ADC to a value appreciably less than 2 to avoid clipping of the output caused by over-ranging also can reduce the accuracy of the pipeline ADC, and in fact is likely to prevent the digital output of the pipeline ADC from ever attaining all “0”s (and values very close thereto), and also from ever attaining all “1”s (and values very close thereto).
Another major problem of the self-calibrating pipeline ADC of the '027 patent is that the disclosed structure necessarily creates a substantial number of lost digital codes near minimum-scale and full-scale digital outputs. This occurs as a result of the disclosed technique of reducing the gain G of the individual bit stages being self-calibrated, to a value substantially less than 2 in order to avoid clipping of the digital output signal in response to minimum scale and maximum scale values of the analog input signal Vin. This problem can be understood by referring to
FIG. 6
of the '027 patent and associated text. The problem results from the described subtracting technique for subtracting calibration constants from values of the digital output which a

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