Digitally controlled trim circuit

Details Digitally controlled trim circuit Digitally controlled trim circuit

1996-11-21

1998-11-17

Shoop, Jr., William M.

Electrical transmission or interconnection systems

Switching systems

Plural switches

307125, 326 49, 327525, H03K 301, H01H 1914

Patent

active

058380760

ABSTRACT:
A digitally controlled trim circuit which includes a plurality of resistors connected in series between a circuit node and a reference voltage, a plurality of first solid-state switches (e.g., PMOS transistors) connected in series across respective ones of the resistors, a plurality of multiplexers each having an output coupled to the gate electrode of a respective one of the first switches, a plurality of first control lines coupled to a first input of respective ones of the multiplexers, a plurality of second control lines coupled to a second input of respective ones of the multiplexers, and a plurality of fuses coupled to respective ones of the first control lines. The trim circuit is operable in a trim test mode in response to a first logic level of a select control signal coupled to the select input of each of the multiplexers, and is operable in a fuse-program mode in response to a second logic level of the select control signal.
When the trim circuit is operating in the trim test mode, different combinations of the resistors can be selectively shorted in response to a plurality of trim control bits coupled to the second input of respective ones of the multiplexers. The trim control bits can be stored in a trim register whose contents can be selectively changed to thereby short different combinations of the resistors. When the trim circuit is operating in the fuse-program mode, a selected combination of the resistors can be selected to remain in series by blowing selected ones of the fuses. Preferably, respective ones of the control lines coupled to the selected ones of the fuses which are blown are driven to a first voltage level, e.g., by a pull-down circuit includes a plurality of second solid-state switches (e.g., NMOS transistors) coupled to respective ones of the control lines.

REFERENCES:
patent: 4673866 (1987-06-01), Masuda
patent: 5361001 (1994-11-01), Stolfa
patent: 5381034 (1995-01-01), Thrower et al.
patent: 5412594 (1995-05-01), Moyal et al.
patent: 5459684 (1995-10-01), Nakamura et al.

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