Digitally controlled timing recovery loop with low intrinsic jit

Details Digitally controlled timing recovery loop with low intrinsic jit Digitally controlled timing recovery loop with low intrinsic jit

1991-09-09

1992-10-27

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 11, 331 25, H03L 7089, H03L 7091, H03L 7093

Patent

active

051592916

ABSTRACT:
A timing recovery loop comprising a multi-point sampling phase comparator 10, a data independent smoothing filter 12, a command sequencer 14, a digitally controlled ring oscillator with clock phase selection 16, a clock divider 18, a sampling clock generation control 20, a bandwidth controlling filter 166, a sequential prioritizer 168, a quarter bit detector 170, and a filter 172. The timing recovery loop has a triple loop structure for improved jitter tolerance and bandwidth control. All three loops share the common components of the ring oscillator 16, the clock divider 18, the sampling clock generation 20, the sampling phase comparator 10, and the command sequencer 14. The remaining components are used among one or more of the loops.

REFERENCES:
patent: 4855683 (1989-08-01), Troudet et al.
patent: 4975660 (1990-12-01), Svenson

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