Digitally controlled timing recovery loop

Details Digitally controlled timing recovery loop Digitally controlled timing recovery loop

1990-11-13

1991-11-26

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

307516, 328133, 328155, 331 11, 331 17, 331 25, 331 27, 331 34, 331 57, 375120, H03K 526, H03L 7087, H03L 7091, H03L 7093

Patent

active

050686283

ABSTRACT:
A digitally controlled timing recovery loop is comprised of a digitally controlled Phase Locked Loop (PLL) consisting of a phase detector, loop filter, and voltage controlled oscillator (VCO). The phase detector is a multi-point sampling phase comparator. The loop filter is comprised of a data independent smoothing filter and a command sequencer. The VCO is a digitally controlled ring oscillator with clock phase selection. The timing recovery loop tolerates a relatively large amount of incoming jitter and minimizes data dependent, ISI-induced, intrinsic jitter.

REFERENCES:
patent: 3579122 (1971-05-01), Paine et al.
patent: 3731219 (1973-05-01), Mader et al.
patent: 4091335 (1978-05-01), Giolma et al.
patent: 4270183 (1981-05-01), Robinson et al.
patent: 4584695 (1986-04-01), Wong et al.
patent: 4975660 (1990-12-01), Svenson

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