Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Patent
1997-10-30
2000-02-22
Kinkead, Arnold
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
331 57, 331 36C, 331 74, 331 34, 327156, 327159, H03B 524
Patent
active
060284889
ABSTRACT:
A digitally-controlled oscillator (DCO) (60), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO (60) is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (40). Each of capacitors (40) has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger (42) that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic (38, 39) that inverts the common node of the capacitors (40). The switching time at the input of Schmitt trigger (42) depends upon the variable load presented by the array of switched capacitors (40), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (60). A digital phase-locked loop (PLL) clock generator circuit (50) including a phase detector (64), digital loop filter (62) in combination with the DCO (60), and a programmable frequency divider (66) providing a feedback path from the output of the DCO (60) to the phase detector (64), is also disclosed. The PLL clock generator (50) may be used in an integrated circuit such as a digital signal processor (30) or microprocessor, and is particularly well-suited for use in a battery-powered portable electronic system (200).
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Dunning et al., "An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors", J. Solid State Circ. (IEEE, Apr. 1995), pp. 412-422.
F. Lu, H. Samueli, J. Yuan, and C. Svensson, "A 700-MHz 24-b Pipelined Accumulator in 1.2-um CMOS for Applications as a Numerically Controlled Oscillator," IEEE Journal of Solid-State Circuits, vol. 28, No. 8 (IEEE, Aug. 1993), pp. 878-886.
D.-K. Jeong, G. Borriello, D. Hodges, and R. Katz, "Design of PLL-Based Clock Generation Circuits," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2 (Apr. 1987), pp. 255-261.
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Fattaruso John W.
Landman Paul E.
Lee Wai
Brady III Wade J.
Donaldson Richard L.
Kinkead Arnold
Neerings Ronald O.
Texas Instruments Incorporated
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