Digitally-controlled L-C oscillator

Details Digitally-controlled L-C oscillator Digitally-controlled L-C oscillator

2000-10-05

2003-12-09

Kinkead, Arnold (Department: 2817)

Geometrical instruments

Area integrators

Electrical

C331S17700V, C331S03600C, C331S167000, C331S1170FE, C327S156000, C327S159000

Reexamination Certificate

active

06658748

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to voltage controlled oscillators, and more particularly to a fully digitally-controlled LC tank oscillator (DCO) that employs one or more banks of more significant binary-weighted and/or less significant equally-weighted capacitors in which certain less significant capacitors are dithered between only two voltage potentials to increase the resolution of desired less significant capacitors.
2. Description of the Prior Art
Operating clock rates of modern VLSI circuits, such as microprocessors and digital signal processors (DSPs), have increased greatly over recent years. These clock rates, now up to on the order of GHz, and the corresponding increase in the number of operations that can be performed over time by the VLSI circuits, have provided dramatic increases in the functionality of electronic computing systems, including mobile, battery-powered, systems such as notebook computers, wireless telephones, and the like. In order to provide such high speed functionality, functions such as on-chip clock generation and clock recovery (i.e., generation of timing information from serial bitstreams) must of course operate at these high frequencies.
As related to clock generation, the increase in clock frequencies has in turn made the timing constraints for communication among the various integrated circuits more stringent. Particularly in systems that utilize synchronous operation and data communication among multiple integrated circuits, the timing skew between external system clocks and the internal clocks that control the operation of the integrated must be reduced to very small margins.
Conventional systems generally utilize analog PLLs for on-chip generation and synchronization of internal clock signals from system reference clocks. Typical analog PLLs include a phase detector that compares the phase relationship of the reference clock to an internal clock, a charge pump and loop filter for setting an analog voltage corresponding to this phase relationship, and a voltage-controlled oscillator (VCO) for generating an output clock signal in response to the analog voltage from the charge pump and loop filter. In recent years, digital phase detectors have been used in on-chip PLLs in combination with the analog charge pump and filter, and the analog VCO; such PLLs have been referred to as “digital”, but of course in reality these PLLs are hybrid digital and analog circuits.
Recently, efforts have been made toward the development of fully digital PLLs. In combination with a digital phase detector, fully digital PLLs include a digital loop filter instead of the traditional analog filter, and include a digitally-controlled oscillator instead of the voltage controlled oscillator. In theory, these fully digital PLLs have several advantages over their analog counterparts. First, digital logic exhibits much better noise immunity than analog circuitry. Second, analog components are vulnerable to DC offset and drift phenomena that are not present in equivalent digital implementations. Further, the loop dynamics of analog PLLs are quite sensitive to process technology scaling; whereas the behavior of digital logic remains unchanged with scaling. This requires much more significant redesign effort to migrate analog PLLs to a new technology node than is required for digital PLLs.
Moreover, power dissipation is of extreme concern for portable, battery-powered, computing systems, as power dissipation relates directly to battery life. As a result, many manufacturers are reducing the power supply voltage requirements of the integrated circuits, particularly those that are specially adapted for portable computing systems, to reduce the power consumed by these devices. It has been observed however, that a reduction in the power supply voltage applied to analog circuitry, such as analog or hybrid PLLs, does not necessarily reduce the power dissipated by these circuits; in some cases, aggressive voltage scaling has been observed to increase the power dissipated by analog circuits. Additionally, reduction in the power supply voltage to analog circuits renders the design of robust circuits much more difficult, given the reduced available “headroom” for the circuits.
In view of the foregoing, PLLs in which digital techniques are used in not only the phase detector, but also in the loop filter and the controllable oscillator, are very attractive to designers. In particular, and as noted above, the implementation of fully digital PLLs to include a digitally-controlled oscillator (DCO), which is an oscillator that operates at a frequency controlled by the value of a digital control word applied thereto, has become especially attractive.
As is known in the art, high frequency circuits other than clock generation circuits also may benefit from the implementation of an all-digital PLL. For example, as noted above, the function of clock recovery (i.e., the extraction of timing information and synchronization from a serial bitstream) is common in effecting high-frequency data communication among integrated circuits and systems. It is, of course, desirable to communicate data at as high a frequency as possible, and as such the frequencies at which clock recovery circuitry are to operate are ever-increasing. Further, considering that communication is a primary function in many battery-powered systems, such as wireless telephones, wireless modems in portable computers, and the like, it is desirable to reduce power dissipation and, consequently, the supply voltage required to implement clock recovery circuits, along with increasing the frequency of operation thereof. As such, many of the advantages provided by fully digital PLLs and the DCOs associated therewith are also beneficial to clock recovery circuits, as well as other applications in modern integrated circuits. The utility of the DCO however, is not limited to PLL applications. In fact, it is contemplated that any application requiring a frequency-programmable oscillator has the potential to benefit from an efficient implementation of a DCO.
The fundamental function of a DCO is to provide an output waveform that has a frequency of oscillation ƒ
DCO
that is a function of a digital input word D, as follows:
ƒ
DCO
=ƒ(
D
)=ƒ(
d
n−1
·2
n−1
+d
n−2
·2
n−2
+ . . . +d
1
·2
1
+d
0
·2
0
)
Typically, the DCO transfer function ƒ( . . . ) is defined so that either the frequency ƒ
DCO
or the period of oscillation T
DCO
is linear with D, generally with an offset. A DCO transfer function, for example, that is linear in frequency is typically expressed as:
ƒ(
D
)=ƒ
offset
+D·ƒ
step
where ƒ
offset
is a constant offset frequency and ƒ
step
is the frequency quantization step. Similarly, a DCO transfer function that is linear in period is typically expressed as
T
(
D
)=1/ƒ(
D
)≈
T
offset
−D·T
step
where T
offset
is a constant offset period and T
step
is the period quantization step. It is of course evident that, since the DCO period T(D) is a function of a quantized digital input D, the DCO cannot generate a continuous range of frequencies, but rather produces a finite number of discrete frequencies.
One common type of conventional DCO includes a high-frequency oscillator in combination with a dynamically programmable frequency divider. An example of this type of DCO is illustrated in
FIG. 1
a
. In this example, programmable frequency divider
2
receives an n-bit digital word D which indicates the divisor value at which the frequency of the output signal HFCLK of high-frequency oscillator
4
is to be divided in generating the DCO output signal CLK. In this conventional arrangement, the period quantization step T
step
, and thus the lower bound of the timing jitter, is limited to the period of high-frequency oscillator
4
. Low jitter operation thus requires oscillator
4
to operate at an extremely high frequency; for example, a 0.2 nsec ste

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